Soft UV-NIL at 20 nm scale using flexible bi-layer stamp casted on HSQ master mold

In this paper we present a comparative study of two e-Beam Lithography (EBL) processes for Nanoimprinting Lithography (NIL) master mold, i.e. the standard PMMA based EBL Si patterning process and the HSQ process. 20 nm features with minimal sidewall roughness and high uniformity are demonstrated on large surface by using HSQ process. Moreover, to validate this ultra-high resolution HSQ EBL process and to check NIL resolution performances, soft UV-NIL replications were performed using soft hard-PDMS/PDMS bi-layer stamps casted on the HSQ master mold. We demonstrate the replication of sub-20 nm nanodots of high density (pitch 60 nm) with a good uniformity on the whole field area.     

Capacitance DNA bio-chips improved by new probe immobilization strategies

Label-free DNA detection plays a crucial role in developing point-of-care biochips. Capacitance detection is a promising technology for label-free detection. However, data published in literature often show evident time drift, large standard deviation, scattered data points, and poor reproducibility. To address these problems, mercapto-hexanol or similar alkanethiols are usually considered as blocking agents. The aim of the present paper is to investigate new blocking agents to further improve DNA probe surfaces. Data from AFM, SPR, florescence microscopy, and capacitance measurements are used to investigate new lipoate and ethylene-glycol molecules. The new surfaces offer further improvements in terms of diminished detection errors. Film structures are investigated at the nano-scale to justify the detection improvements in terms of probe surface quality. This study demonstrates the superiority of lipoate and ethylene-glycol molecules as blocking candidates when immobilizing molecular probes onto spot surfaces in label-free DNA biochip.     

Environmentally Friendly Graphene Inks for Touch Screen Sensors

Graphene-based materials have attracted significant attention in many technological fields, but scaling up graphene-based technologies still faces substantial challenges. High-throughput top-down methods generally require hazardous, toxic, and high-boiling-point solvents. Here, an efficient and inexpensive strategy is proposed to produce graphene dispersions by liquid-phase exfoliation (LPE) through a combination of shear-mixing (SM) and tip sonication (TS) techniques, yielding highly concentrated graphene inks compatible with spray coating. The quality of graphene flakes (e.g., lateral size and thickness) and their concentration in the dispersions are compared using different spectroscopic and microscopy techniques. Several approaches (individual SM and TS, and their combination) are tested in three solvents (N-methyl-2-pyrrolidone, dimethylformamide, and cyrene). Interestingly, the combination of SM and TS in cyrene yields high-quality graphene dispersions, overcoming the environmental issues linked to the other two solvents. Starting from the cyrene dispersion, a graphene-based ink is prepared to spray-coat flexible electrodes and assemble a touch screen prototype. The electrodes feature a low sheet resistance (290 Ω □⁻¹) and high optical transmittance (78%), which provide the prototype with a high signal-to-noise ratio (14 dB) and multi-touch functionality (up to four simultaneous touches). These results illustrate a potential pathway toward the integration of LPE-graphene in commercial flexible electronics.     

Integration of InGaP/GaAs/Ge triple‐junction solar cells on deeply patterned silicon substrates

We report preliminary results on InGaP/InGaAs/Ge photovoltaic cells for concentrated terrestrial applications, monolithically integrated on engineered Si(001) substrates. Cells deposited on planar Ge/Si(001) epilayers, grown by plasma‐enhanced chemical vapor deposition, provide good efficiency and spectral response, despite the small thickness of the Ge epilayers and a threading dislocation density as large as 10⁷/cm². The presence of microcracks generated by the thermal misfit is compensated by a dense collection grid that avoids insulated areas. In order to avoid the excessive shadowing introduced by the use of a dense grid, the crack density needs to be lowered. Here, we show that deep patterning of the Si substrate in blocks can be an option, provided that a continuous Ge layer is formed at the top, and it is suitably planarized before the metalorganic chemical vapor deposition. The crack density is effectively decreased, despite that the efficiency is also lowered with respect to unpatterned devices. The reasons of this efficiency reduction are discussed, and a strategy for improvement is proposed and explored. Full morphological analysis of the coalesced Ge blocks is reported, and the final devices are tested under concentrated AM1.5D spectrum. Copyright © 2016 John Wiley & Sons, Ltd.     

CMOS-Compatible Room-Temperature Rectifier Toward Terahertz Radiation Detection

In this paper, we present a new rectifying device, compatible with the technology of CMOS image sensors, suitable for implementing a direct-conversion detector operating at room temperature for operation at up to terahertz frequencies. The rectifying device can be obtained by introducing some simple modifications of the charge-storage well in conventional CMOS integrated circuits, making the proposed solution easy to integrate with the existing imaging systems. The rectifying device is combined with the different elements of the detector, composed of a 3D high-performance antenna and a charge-storage well. In particular, its position just below the edge of the 3D antenna takes maximum advantage of the high electric field concentrated by the antenna itself. In addition, the proposed structure ensures the integrity of the charge-storage well of the detector. In the structure, it is not necessary to use very scaled and costly technological nodes, since the CMOS transistor only provides the necessary integrated readout electronics. On-wafer measurements of RF characteristics of the designed junction are reported and discussed. The overall performances of the entire detector in terms of noise equivalent power (NEP) are evaluated by combining low-frequency measurements of the rectifier with numerical simulations of the 3D antenna and the semiconductor structure at 1 THz, allowing prediction of the achievable NEP.     

嵌入式系统软件调试跟踪技术的发展趋势

在过去的几十年里，嵌入式工程师在开发和调试中已经越来越依赖于跟踪缓存的帮助。但随着100MHz频率以上的高速RISC处理器的普及，片内Cache、RAM和FLASH存储器逐渐变得越来越普遍。越来越多的处理器总线活动将无法在外部管脚上观测。这样，传统的收集跟踪信息的方法就不再可行了。     

Reduced Impact of Induced Gate Noise on Inductively Degenerated LNAs in Deep Submicron CMOS Technologies

Designers of radio-frequency inductively-degenerated CMOS low-noise-amplifiers have usually not followed the guidelines for achieving minimum noise figure. Nonetheless, state-of-the-art implementations display noise figure values very close to the theoretical minimum. In this paper, we point out that this is due to the effect of the parasitic overlap capacitances in the MOS device. In particular, we show that overlap capacitances lead to a significant induced-gate-noise reduction, especially when deep sub-micron CMOS processes are used.Paolo Rossi was born in Milan, Italy, in 1975. He received the Laurea degree (summa cum laude) in electrical engineering from the University of Pavia, Pavia, Italy, in 2000, where he is currently working toward the Ph.D. degree. His research interests are in the field of analog integrated circuits for wireless transceivers in CMOS and BiCMOS technology, with particular focus on the analysis and design of LNA and mixer for multi-standard applications.Francesco Svelto received the Laurea and Ph.D. degrees in electrical engineering from the University of Pavia, Pavia, Italy, in 1991 and 1995, respectively. From 1996 to 1997, he held a grant from STMicroelectronics to design CMOS RF circuits. In 1997, he was appointed Assistant Professor at the University of Bergamo, Italy, and in 2000, he joined the University of Pavia, where he is an Associate Professor. His current research interests are in the field of RF design and high-frequency integrated circuits for telecommunications. Dr. Svelto has been a member of the technical program committee of the IEEE Custom Integrated Circuits Conference since 2000 and the Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) since 2003, and the European Solid State Circuits Conference in 2002. He served as Guest Editor of the March 2003 special issue of the IEEE Journal of Solid-State Circuits, of which he is currently an Associate Editor.Andrea Mazzanti was born in Modena (Italy) in 1976. He received the Laurea degree (summa cum Laude) in Electrical Engineering from the University of Modena and Reggio Emilia, Modena, Italy in 2001. Since 2001 he is pursuing his PhD in Electrical Engineering at University of Modena and Reggio Emilia, Italy. His major research interest are modelling of microwave semiconductor devices and design of CMOS RF integrated circuits, with particular focus on low noise oscillators and analog frequency dividers. During the summer of 2003 he was with Agere Systems, Allentown, PA as an internship student, working on the design of an highly integrated CMOS FM transmitter.Pietro Andreani received the M.S.E.E. from the University of Pisa, Italy, in 1988. He joined the Dept. of Applied Electronics, Lund University, Sweden, in 1990, where he contributed to the development of software tools for digital ASIC design. After working at the Dept. of Applied Electronics, University of Pisa, as a CMOS IC designer during 1994, he rejoined the Dept. of Applied Electronics in Lund as an Associate Professor, where he was responsible for the analog IC course package between 1995 and 2001, and where he received the Ph.D. degree in 1999. He is currently a Professor at the Center for Physical Electronics, ØrstedDTU, Technical University of Denmark, Kgs. Lyngby, Denmark, with analog/RF CMOS IC design as main research field.     

A time Petri net-based method for embedded hard real-time software synthesis

Over the last few years, embedded software synthesis has drawn much attention. However, few works deal with software synthesis for hard real-time systems considering arbitrary inter-tasks precedence and exclusion relations. Code generation for meeting all timing and resource constraints is not a trivial task. Thus, this research area has several open issues, mainly related to generation of predictable-guaranteed scheduled code. The method proposed in this paper starts from a high-level specification, and automatically translates such specification into a time Petri net model; this model is adopted for finding a feasible static schedule meeting all constraints. If found, the approach generates a scheduled code, based on the found feasible schedule. Therefore, the user just enter the specification and receives, as result, the scheduled code. Thus, all intermediary phases are hidden from the users.     

Slot Routing as a Solution for Optically Transparent Scalable WDM Wide Area Networks*

All-optical Wavelength Division Multiplexing (WDM) backbones are believed to be a fundamental component in future high speed networks. Currently, the most pursued approach for Wide Area Networks (WANs) is wavelength routing, in which communication circuits are established between node pairs by means of lightpaths (paths of light) spanning one or more fiber-optic links. This approach has, however, two drawbacks. Since the number of wavelengths and links in a network is finite, not all node pairs can be connected via a dedicated lightpath directly. Consequently, some node pairs will communicate using a concatenation of lightpaths, which requires electronic switching of in transit information, loosing the advantages of optical transparency. Secondly, typically some form of (electronic) traffic grooming will be necessary to make efficient use of the fixed lightpath capacity. This paper proposes to design all-optical WANs using a novel approach, called photonic slot routing. With photonic slot routing, entire slots, each carrying multiple packets on distinct wavelengths, are switched transparently and individually, using available fast and wavelength non-sensitive devices. The advantage of using photonic slot routing is threefold. All node pairs in the network communicate all-optically. Traffic aggregation necessary to efficiently use the capacity of the wavelength channels is optically achieved. The solution is practical as it is based on proven optical technologies. In addition, through the use of wavelength non-sensitive devices the proposed WAN design yields intrinsic scalability in the number of wavelengths.