New two CFOA-based sinusoidal RC oscillators with buffered outlet

Using a unified representation for a class of buffered-outlet two current-feedback operational amplifier (CFOAs)-based sinusoidal oscillators, new circuits of this type can be systematically discovered. A catalogue of four circuit structures, each structure realizing nine oscillator circuits, is presented. Moreover, using the RC:CR transformation, additional nine oscillator circuits can be obtained from each structure. While each circuit requires five passive elements, some of the circuits enjoy one or more of the following attractive features: use of grounded capacitors, feasibility of absorbing the parasitic components of the CFOAs and orthogonal tuning of the frequency and the startup condition of oscillation.     

Collaborative and Cognitive Network Platforms: Vision and Research Challenges

In this paper, we present a visionary concept referred to as Collaborative and Cognitive Network Platforms (CCNPs) as a future-proof solution for creating a dependable, self-organizing and self-managing communication substrate for effective ICT solutions to societal problems. CCNP creates a cooperative communication platform to support critical services across a range of business sectors. CCNP is based on the personal network (PN) technology which is an inherently cooperative environment prototyped in the Dutch Freeband PNP2008 and the European Union IST MAGNET projects. In CCNP, the cognitive control plane strives to exploit the resources to better satisfy the requirements of networked applications. CCNP facilitates collaboration inherently. Through cognition in the cognitive control plane, CCNP becomes a self-managed substrate. The self-managed substrate, in this paper, is defined as cognitive and collaborative middleware on which future applications run without user intervention. Endemic sensor networks may be incorporated into the CCNP concept to feed its cognitive control plane. In this paper, we present the CCNP concept and discuss the research challenges related to collaboration and cognition.     

Accelerating Machine-Learning Algorithms on FPGAs using Pattern-Based Decomposition

Machine-learning algorithms are employed in a wide variety of applications to extract useful information from data sets, and many are known to suffer from super-linear increases in computational time with increasing data size and number of signals being processed (data dimension). Certain principal machine-learning algorithms are commonly found embedded in larger detection, estimation, or classification operations. Three such principal algorithms are the Parzen window-based, non-parametric estimation of Probability Density Functions (PDFs), K-means clustering and correlation. Because they form an integral part of numerous machine-learning applications, fast and efficient execution of these algorithms is extremely desirable. FPGA-based reconfigurable computing (RC) has been successfully used to accelerate computationally intensive problems in a wide variety of scientific domains to achieve speedup over traditional software implementations. However, this potential benefit is quite often not fully realized because creating efficient FPGA designs is generally carried out in a laborious, case-specific manner requiring a great amount of redundant time and effort. In this paper, an approach using pattern-based decomposition for algorithm acceleration on FPGAs is proposed that offers significant increases in productivity via design reusability. Using this approach, we design, analyze, and implement a multi-dimensional PDF estimation algorithm using Gaussian kernels on FPGAs. First, the algorithm’s amenability to a hardware paradigm and expected speedups are predicted. After implementation, actual speedup and performance metrics are compared to the predictions, showing speedup on the order of 20× over a 3.2 GHz processor. Multi-core architectures are developed to further improve performance by scaling the design. Portability of the hardware design across multiple FPGA platforms is also analyzed. After implementing the PDF algorithm, the value of pattern-based decomposition to support reuse is demonstrated by rapid development of the K-means and correlation algorithms.     

Low Complexity Time Domain Interleaved Partitioning Partial Transmit Sequence Scheme for Peak-to-Average Power Ratio Reduction of Orthogonal Frequency Division Multiplexing Systems

As an attractive technique for peak-to-average power ratio (PAPR) reduction in orthogonal frequency division multiplexing (OFDM) systems, time domain interleaved partitioning partial transmit sequence (TD-IP-PTS) scheme uses circular convolution property of discrete Fourier transforms (DFT) so as to need only one inverse fast Fourier transform (IFFT) operation. However, the search and combination of phase factors still need higher computational complexity. In order to improve the problem, this paper detailedly analyzes the independence of phase factor vectors and optimizes the phase factor vectors in TD-IP-PTS. Furthermore, we find the characteristic of combination of phase factors and propose three methods respectively based on storage-unit, pipeline and select-path to implement the combination of phase factors in TD-IP-PTS. The simulation results show that TD-IP-PTS using independent and effective phase factor vectors has better PAPR performance and lower complexity than traditional IP-PTS. Moreover, among three proposed methods for combination of phase factors, the method based on select-path requires the least registers and delay time. This method is the most promising in practical applications.     

FPGA Architecture for 2D Discrete Fourier Transform Based on 2D Decomposition for Large-sized Data

Applications based on Discrete Fourier Transforms (DFT) are extensively used in several areas of signal and digital image processing. Of particular interest is the two-dimensional (2D) DFT which is more computation- and bandwidth-intensive than the one-dimensional (1D) DFT. Traditionally, a 2D DFT is computed using Row-Column (RC) decomposition, where 1D DFTs are computed along the rows followed by 1D DFTs along the columns. Both application specific and reconfigurable hardware have utilized this scheme for high-performance implementations of 2D DFT. However, architectures based on RC decomposition are not efficient for large input size data due to memory bandwidth constraints. In this paper, we propose an efficient architecture to implement 2D DFT for large-sized input data based on a novel 2D decomposition algorithm. This architecture achieves very high throughput by exploiting the inherent parallelism due to the algorithm decomposition and by utilizing the row-wise burst access pattern of the external memory. A high throughput memory interface has been designed to enable maximum utilization of the memory bandwidth. In addition, an automatic system generator is provided for mapping this architecture onto a reconfigurable platform of Xilinx Virtex-5 devices. For a 2K ×2K input size, the proposed architecture is 1.96 times faster than RC decomposition based implementation under the same memory constraints, and also outperforms other existing implementations.     

Fast computation of wideband RCS using characteristic basis function method and asymptotic waveform evaluation technique

The Asymptotic Waveform Evaluation (AWE) technique is an extrapolation method that provides a reduced-order model of linear system and has already been successfully used to analyze wideband electromagnetic scattering problems. As the number of unknowns increases, the size of Method Of Moments (MOM) impedance matrix grows very rapidly, so it is a prohibitive task for the computation of wideband Radar Cross Section (RCS) from electrically large object or multi-objects using the traditional AWE technique that needs to solve directly matrix inversion. In this paper, an AWE technique based on the Characteristic Basis Function (CBF) method, which can reduce the matrix size to a manageable size for direct matrix inversion, is proposed to analyze electromagnetic scattering from multi-objects over a given frequency band. Numerical examples are presented to illustrate the computational accuracy and efficiency of the proposed method.     

Impairment-aware ordered scheduling in dual-header optical burst switched networks

Optical burst switching (OBS) is a promising technology for bridging the gap between optical wavelength switching and optical packet switching. Optical signal transmission quality is subject to various types of physical impairment introduced by optical fibers, switching elements, or other network components. The signal degradation due to physical impairment may be significant enough such that the bit-error rate of received signals is unacceptably high at the destination, rendering the signal to not usable. In this article, based on earlier study, we study the burst-scheduling problem in OBS networks using two control packets for each data burst, taking into account physical impairment effects. We propose a burst-scheduling algorithm that accommodates incoming bursts by primary path routing, deflection routing, and burst scheduling. We design an admission control mechanism to use network resources efficiently. At an OBS node, the proposed algorithm schedules bursts for transmission by searching for available resources as well as verifying signal quality. Our simulation results demonstrate that the proposed algorithm is effective in terms of reducing the burst-blocking probability.     

Systematic design of wideband ΔΣ modulators for WiFi/WiMAX receivers

Modern multi-standard receivers in deep-submicron technologies pose significant design challenges on the analog baseband. Moving this analog filtering to the digital domain simplifies the design, yielding a process-scalable implementation. However, analog-to-digital converter (ADC) specifications now become more stringent and must be obtained by comprehending the standard and the system. Assuming a receiver NF of 5.96 dB and SNR degradation of 0.36 dB by the ADC, the proposed dual-mode WiFi/WiMAX receiver attains an input sensitivity of −74 dBm (20 MHz channel bandwidth). To accommodate the high dynamic range and the anti-alias rejection needed for the system, a Delta-Sigma (ΔΣ) ADC is proposed. Single-loop and Multi-Stage Noise-Shaping (MASH) architectures that achieve a SNR of 69 dB at a low oversampling ratio (OSR) of 8 for a conversion bandwidth of 40 MHz (108 Mbps, OFDM) are investigated at system level. Based on thermal noise, harmonic distortion, and power tradeoffs, a ΔΣ ADC design that meets the design specifications is presented.