A graphic approach to performance analysis of multistage linear interference canceller in long-code CDMA systems

The signal-to-interference-plus-noise-ratio performance of the multistage linear parallel and successive interference cancellers (LPIC and LSIC) in a long-code code-division multiple-access system is analyzed using a graphical approach. The decision statistic is modeled as a Gaussian random variable, whose mean and variance can be expressed as functions of moments of R for the LPIC and L for the LSIC, respectively, where R is the correlation matrix of signature sequences and L is the strict lower triangular part of R. Since the complexity of calculating these moments increases rapidly with the growth of the stage index, a graphical representation of moments is developed to facilitate the computation. Propositions are presented to relate the moment calculation problem to several well-known problems in graph theory, i.e., the coloring, the graph decomposition, the biconnected component finding, and the Euler tour problems. It is shown that the derived analytic results match well with simulation results.     

A CMOS line driver for ADSL central office applications

An ADSL central office (CO) line driver utilizing a single 6-V supply is described. The line driver output produces a 20-V/sub ppd/ signal to deliver a 40-V/sub ppd/ swing to a 100-/spl Omega/ line. The adoption of an active termination, a dynamic supply control circuit technique, and deep n-well devices at the output stage of the line driver is key in achieving such a large voltage swing in a 0.25-/spl mu/m CMOS process. In order to ensure reliability of the output devices, the dynamic supply control algorithm is designed to activate only one lift amplifier at each signal path of the differential line driver at any given time. A transformer turns ratio of 1:2.4 ensures both reliability and optimal power dissipation in the presence of system losses. The total power dissipation of the line driver is 700 mW when discrete multitone signals with a crest factor of 15 dB were used to deliver 20.4 dBm to a 100-/spl Omega/ line.     

Analysis and characterization of traveling-wave electrode in electroabsorption modulator for radio-on-fiber application

Comparing with a lumped electroabsorption modulator (EAM), we show the merits of a long EAM with traveling-wave electrode with high radio-frequency (RF) gain that could be used in high-frequency analog application. By terminating the RF output port with the characteristic impedance of 30 /spl Omega/, the device exhibited a large enhancement of 6 dB above 10 GHz in the electrical-to-optical response and a wide fractional bandwidth as estimated from simulation. In addition, an input impedance matching circuit of stub embedded on the device chip was found to be very effective for improving RF characteristics in the narrow band of frequency.     

Polarity control of GaN epilayers grown on ZnO templates

We report the successful growth of Ga-polar GaN epilayers on O-polar ZnO templates pre-deposited on c-sapphire. Prior to GaN growth, NH₃ is exposed onto the ZnO template. The polarity of the GaN layers is confirmed by etching of the surface and by conversion beam electron diffraction (CBED), while the O-polar ZnO is confirmed by CBED. It is suggested that the NH₃ pre-exposure helps form a Zn₃N₂ layer, which possesses inversion symmetry and inverts the crystal from anion polar to cation polar.     

On the Mechanisms Governing Aluminum-Mediated Solid-Phase Epitaxy of Silicon

Mechanisms governing the aluminum-mediated solid-phase epitaxy of Si on patterned crystalline Si substrates have been identified by studying the deposited material as a function of growth conditions when varying parameters such as temperature, growth time, and layer-stack properties. Early growth stages can be discerned as first formation of “free” Si at the Al/α-Si interface, then diffusion of Si along the Al grain boundaries, nucleation at the Si substrate surface, nuclei rearrangement, and finally crystal growth. The acquired understanding is applied to control the selectivity and completeness of single-crystal growth in various sizes of contact windows to the Si substrate.     

Annealing effect on physical and electrical characteristics of thin HfO2, HfSixOy and HfOyNz films on Si

We report the effect of annealing on electrical and physical characteristics of HfO₂, HfSi_xO_y and HfO_yN_z gate oxide films on Si. Having the largest thickness change of 0.3 nm after post deposition annealing (PDA), HfO_yN_z shows the lowest leakage current. It was found for both as-grown and annealed structures that Poole-Frenkel conduction is dominant at low field while Fowler-Nordheim tunneling in high field. Spectroscopic ellipsometry measurement revealed that the PDA process decreases the bandgap of the dielectric layers. We found that a decreasing of peak intensity in the middle HfO_yN_z layer as measured by Tof-SIMS may suggest the movement of N toward the interface region between the HfO_yN_z layer and the Si substrate during the annealing process.     

Surface leakage current analysis of ion implanted ZnS-passivated n-on-p HgCdTe diodes in weak inversion

Effects of fixed charge on R₀A value of ZnS-passivated x=0.3 HgCdTe n-on-p diode are explained as a shunt resistance that affects current-voltage (I-V) and dynamic resistance-voltage (Rd-V) characteristics. The fixed charge of 1×10¹¹/cm² to 2 × 10¹¹/cm² which is usually obtained with ZnS passivation makes the surface weakly inverted and reduces HgCdTe diode R₀A value owing to the short generation lifetime of HgCdTe substrate. The gate-controlled diode and specially fabricated diode are used to explain the surface leakage current in the weak inversion and charge sheet model is used to explain the characteristics. It is found that the surface leakage current by the inverted channel in the weak inversion can reduce R₀A more than other currents such as the generation current and tunneling current which are usually used to explain the surface leakage current of HgCdTe diode.     

The leakage current improvement in an ultrashallow junction NMOSwith Co silicided source and drain

The leakage current characteristics of the cobalt silicided NMOS transistors with a junction depth of 800 Å have been studied. In order to minimize the junction leakage current, the thickness of the CoSi₂ layer should he controlled under 300 Å and the Si surface damage induced by the gate spacer etch should be minimized. The post furnace annealing after the second silicidation by the rapid thermal annealing (RTA) process also affected the leakage current characteristics. The gate induced drain leakage (GIDL) current was not affected by the lateral encroachment of CoSi₂ layer into the channel direction when the gate spacer length was larger than 400 Å     

Support vector machine-based inspection of solder joints using circular illumination

A method for inspecting solder joints using support vector machines (SVMs) and a tiered circular illumination technique is proposed. The illumination technique provides visual information that allows the 3D shape of the solder joint surface to be determined. The extracted features are used to classify the solder joint using an SVM classifier. Experimental results show the effectiveness of the proposed method.     

Embedded microstrip interconnection lines for gigahertz digitalcircuits

Transmission line structures are needed for the high-performance interconnection lines of GHz integrated circuits (ICs) and multichip modules (MCMs), to minimize undesired electromagnetic wave phenomena and, therefore, to maximize the transmission bandwidth of the interconnection lines. In addition, correct and simple models of the interconnection lines are required for the efficient design and analysis of the circuits containing the interconnection lines. In this paper, we present electrical comparisons of three transmission line structures: conventional metal-insulator-semiconductor (MIS) and the embedded microstrip structures-embedded microstrip (EM) and inverted embedded microstrip (IEM). In addition, we propose closed-form expressions for the embedded microstrip structures EM and IEM and validate the expressions by comparing with empirical results based on S-parameter measurements and subsequent microwave network analysis. Test devices were fabricated using a 1-poly and 3-metal 0.6 μm Si process. The test devices contained the conventional MIS and the two embedded microstrip structures of different sizes. The embedded microstrip structures were shown to carry GHz digital signals with less loss and less dispersion than the conventional MIS line structures. S-parameter measurements of the test devices showed that the embedded microstrip structures could support the quasi-TEM mode propagation at frequencies above 2 GHz. On the other hand, the conventional MIS structure showed slow-wave mode propagation up to 20 GHz. More than 3-dB/mm difference of signal attenuation was observed between the embedded microstrip structures and the conventional MIS structure at 20 GHz. Finally, analytical RLCG transmission line models were developed and shown to agree well with the empirical models deduced from S-parameter measurements