Current-handling and switching performance of MOS-controlledthyristor (MCT) structures

Experimental results are reported for array-type MCT devices fabricated using a BiMOS process with additional power-specific fabrication steps. Stationary measurements of both the thyristor forward behavior and the intrinsic p-channel MOSFET switch characteristics are an indication of the device quality. Through dynamic testing procedures, the device was analyzed in its transient current handling. The combination of anode current and blocking voltage values is the highest ever reported on MCT devices (2 kV, 5 A, in 2 μs)     

Current-kink noise of n-channel enhancement e.s.f.i.-m.o.s. s.o.s. transistors

An experimental study of the low-frequency-noise properties of n-channel epitaxial silicon films on insulator m.o.s. s.o.s. transistors has been performed. The measurements show an excessive noise contribution at drain voltages corresponding to the current-kink effect for temperatures ranging from 4.2 to 300 K.     

Lifetime extrapolation for IGBT modules under realistic operation conditions

In this paper a systematic approach is presented for extrapolating the lifetime due to bond wire lift-off in IGBT modules submitted to cyclic loading. Application profiles of the device are considered, as they are usually encountered in real current converters for railway traction systems. The proposed lifetime prediction scheme is based on the principle of the linear accumulation of the fatigue damage and takes into account the redundancy of the bond wires.     

The development of the German energy market until 2030—A critical survey of selected scenarios

Many scenarios have been generated in the last years analysing the international energy market. The variety of these scenarios is manifold, as they are generated by different institutions using different methodological approaches and different framework assumptions. However, these scenarios can roughly be classified into three main groups: “moderate”, “climate protection” and “resource scarcity and high fossil fuel prices”. Analysing the German energy market makes a fourth scenario group necessary, which considers the possible revision of the decided nuclear energy phase out. Most of the existing scenarios developed by different institutions can be allocated into one of these groups. A representative scenario for each group has been selected to illustrate the development of the energy sector until 2030. Contrary to the worldwide primary energy demand (PED), the German PED decreases in each scenario, even though the drop differs strongly throughout the scenarios. On the other hand the structure of the PED in 2030 varies strongly for each scenario, especially regarding the share of fossil energy sources. However, a common robust result can be observed throughout all scenarios, namely the high increase in the share of the renewable energy resources, although the scenario generation processes are not always robust.     

Synthesis of scanning electron microscopy images by high performance computing for the metrology of advanced CMOS processes

Scanning electron microscopy is still the technique of choice for imaging and for in-line measurement of critical dimensions and overlay accuracy in most of the core technology processes. In particular, critical dimension microscopy provides information about design template matching and edge placement errors through links with design having proven beneficial effects on process yield and product reliability. In this paper, the use of high performance computing is demonstrated to simulate linescans and 2D secondary electron images to be used in optical proximity error correction strategies for nanometer scale technologies.     

Substrate potential shift due to parasitic minority carrier injection in smart-power ICs: measurements and full-chip 3D device simulation

Substrate current injection effects are one of the major risks for smart-power IC functionality, often leading to redesigns. Smart-power ICs for motor control consist of four power transistors in H-bridge configuration and the controlling circuitry on a single chip. During switching of the power stages driving an inductive load (e.g. a motor), parasitic bipolar transistors turn on and inject electrons and holes into the substrate. This leads to a substrate potential shift with the risk of disturbing the functionality of the controlling circuitry or even triggering a latch-up. The substrate potential shift due to minority carrier injection by the lateral parasitic NPN transistor has been measured on a test chip and analyzed by 3D device simulation. The previously calibrated 3D device simulation and the measurements are in good agreement. The influence of protecting measures (substrate contacts) and the backside contact has been investigated experimentally. For the first time, the potential shift due to the parasitic substrate NPN transistor has been measured and simulated in 3D on an entire chip.     

Parasitic modes on printed circuit boards and their effects on EMCand signal integrity

In this paper, parasitic modes, such as slotline, parallel plane, and surface wave (SW) modes, commonly found on printed circuit boards (PCBs) are analyzed and their effects on electromagnetic compatibility (EMC) and signal integrity are discussed. The analysis is based on numerical simulations using the finite difference time domain (FDTD) method which is shown to be very well suited for rigorous modeling of parasitic mode effects. The EMC and signal integrity problems discussed include power loss, crosstalk, ground bounce, and free space radiation. Design guidelines for improved EMC and signal integrity are derived from the results obtained. Comprehensive simulation and characterization of SWs using FDTD is presented for the first time     

Low-power logic styles: CMOS versus pass-transistor logic

Recently reported logic style comparisons based on full-adder circuits claimed complementary pass-transistor logic (CPL) to be much more power-efficient than complementary CMOS. However, new comparisons performed on more efficient CMOS circuit realizations and a wider range of different logic cells, as well as the use of realistic circuit arrangements demonstrate CMOS to be superior to CPL in most cases with respect to speed, area, power dissipation, and power-delay products. An implemented 32-b adder using complementary CMOS has a power-delay product of less than half that of the CPL version. Robustness with respect to voltage scaling and transistor sizing, as well as generality and ease-of-use, are additional advantages of CMOS logic gates, especially when cell-based design and logic synthesis are targeted. This paper shows that complementary CMOS is the logic style of choice for the implementation of arbitrary combinational circuits if low voltage, low power, and small power-delay products are of concern     

Pediatric genitourinary tumors

During the past two decades, highly effective multimodality therapy involving surgery, chemotherapy, and radiation has been developed through consecutive national and international study protocols for childhood genitourinary cancers with the model being Wilms' tumor. These studies represent a landmark achievement in the history of pediatric oncology and mark the success of multi-institutional studies. With the excellent survival rates that have been established, current interest is now directed toward examining survivors for long-term treatment complications and minimizing the side effects while preserving treatment efficacy. In addition, new developments in the molecular biology of Wilms' tumor have made this neoplasm a model for understanding the molecular and genetic aspects of tumorigenesis. This article reviews some of the publications from 1992 on pediatric genitourinary tumors.     

A hot-carrier analysis of submicrometer MOSFET's

Based on Monte Carlo (MC) device simulations, an analysis of hot-carrier effects in submicrometer n-MOSFETs is presented that provides detailed insight because the high-energy electrons are treated directly. The DC stress characteristics of both lightly-doped drain (LDD) and conventional As source/drain devices are found to correlate with the surface hot-electron concentration, and agreement with experimental data shows that the electron flux above 3 eV, integrated along the channel, can be used to predict device degradation. The simulations indicate that the whole DC stress characteristic can be attributed to hot electrons, while the holes generated by impact ionization have a very small probability of gaining enough energy to be injected over the oxide barrier