A 0.18-/spl mu/m SiGe BiCMOS receiver and transmitter chipset for SONET OC-768 transmission systems

A 43-Gb/s receiver (Rx) and transmitter (Tx) chip set for SONET OC-768 transmission systems is reported. Both ICs are implemented in a 0.18-/spl mu/m SiGe BiCMOS technology featuring 120-GHz f/sub T/ and 100 GHz f/sub max/. The Rx includes a limiting amplifier, a half-rate clock and data recovery unit, a 1:4 demultiplexer, a frequency acquisition aid, and a frequency lock detector. Input sensitivity for a bit-error rate less than 10/sup -9/ is 40 mV and jitter generation better than 230 fs rms. The IC dissipates 2.4 W from a -3.6-V supply voltage. The Tx integrates a half-rate clock multiplier unit with a 4:1 multiplexer. Measured clock jitter generation is better than 170 fs rms. The IC consumes 2.3 W from a -3.6-V supply voltage.     

Cascode Monolithic DC-DC Converter for Reliable Operation at High Input Voltages

A CMOS OTA-C low-pass notch filter for EEG application is described. The pass-band covers four bands of brain wave and provides more than 65 dB attenuation for the 50 Hz power line interference. The OTA works in the weak inversion region and a low transconductance of 3 nA/V is achieved. The low transconductance enables using small capacitors in the OTA-C filter so that the filter is suitable for the multi-channel EEG integrated circuits. The measured results show the good performance of the filter for filtering the noise in acquired EEG signals. Xinbo Qian received the B.Sc. degree from Beijing Institute of Technology, P.R. China, in 1991 and M.Sc. degree from Institute of Physics, Chinese Academy of Sciences, in 1996. From 1996 to 1999, she was a research engineer in the Institute of Acoustics, Chinese Academy of Sciences, worked on the sonar signal receiving and processing systems. Since 1999, she has been pursuing the Ph.D. degree in Electrical and Computer Engineering department, National University of Singapore, with research direction on on-chip readout circuits for microbolometer focal plane arrays. Now she is employed by Department of Mechanical Engineering and Division of Bioengineering, National University of Singapore as a research fellow. Her research interest is low-noise integrated circuits design and bio-medical sensor electronics, including electroencephalography IC, magnetocardiography IC, low-noise amplifier, filter and data converters etc. Yong Ping Xu graduated from Nanjing University, P.R. China in 1977. He received his Ph.D. from University of New South Wales (UNSW) Australia, in 1994. From 1978 to 1987, he was with Qingdao Semiconductor Research Institute, P.R. China, initially as an IC design engineer, and later the deputy R&D manager and the Director. From 1989 to 1992, he was working on silicon diode based infrared detectors towards his Ph.D. at School of Electrical Engineering, UNSW Australia. From 1993 to 1995, he worked on an industry collaboration project with GEC Marconi, Sydney, Australia, at the same university, involved in design of sigma-delta ADCs. He was a lecturer at University of South Australia, Adelaide, Australia from 1996 to 1998. He has been with the Department of Electrical and Computer Engineering, National University of Singapore since June 1998 and is now an Associate Professor. His general research interests are in the areas of mixed-signal and RF integrated circuits, and integrated MEMS and sensing systems. His current focuses are high-speed wideband ADC, UWB front-end circuits and low-power low-voltage integrated circuits for biomedical applications. He is a Senior Member of IEEE. Xiaoping Li received his Ph.D. degree from Department of Mechanical and Manufacturing Engineering, University of New South Wales, Australia in 1991, and joined the National University of Singapore in 1992, where he is currently an Associate Professor with the Department of Mechanical Engineering and Division of Bioengineering. He was a visiting professor of Tokyo Institute of Technology, Japan in 2000, and visiting professor of Georgia Institute of Technology, USA in 2001. He is a member of American Society of Mechanical Engineers (ASME), a senior member of Society of Manufacturing Engineering (SME) and a senior member of North American Manufacturing Research Institute/SME, and is currently the Chairman of SME Singapore Chapter. His current research interests include neurosensors and nanomachining. He is a guest editor of International Journal of Computer Applications in Technology, USA. He is a regular reviewer of the ASME Journal of Manufacturing Engineering, USA, Transactions of NAMRI/SME, USA, Journal of materials processing technology, UK, International Journal of Machine Tools and Manufacture, UK, and IMechE Journal of Engineering Manufacture, UK.     

Clock frequency and latency in synchronous digital systems

The tradeoffs in the design of synchronous digital systems between clock frequency and latency in terms of the circuit characteristics of a pipelined data path are described. A design paradigm relating latency and clock frequency as a function of the level of pipelining is developed for studying the performance of a synchronous system. This perspective permits the development of design equations for constrained and unconstrained design problems which describe these performance parameters in terms of the delays of the logic, interconnect, registers, clock skew, and the number of logic states. These results provide an approach to the design of those synchronous digital systems in which latency and clock frequency are of primary importance. From the behavioral specifications for the proposed system, the designer can use these results to select the best logic architecture and the best available device technology to determine if the performance specifications can be satisfied, and, if so, what design options are available for optimization of other system attributes, such as area     

Inductive properties of high-performance power distribution grids

The design of high integrity, area efficient power distribution grids has become of practical importance as the portion of on-chip interconnect resources dedicated to power distribution networks in high performance integrated circuits has greatly increased. The inductive characteristics of several types of gridded power distribution networks are described in this paper. The inductance extraction program FastHenry is used to evaluate the inductive properties of grid structured interconnect. In power distribution grids with alternating power and ground lines, the inductance is shown to vary linearly with grid length and inversely linearly with the number of lines in the grid. The inductance is also relatively constant with frequency in these grid structures. These properties permit the efficient estimation of the inductive characteristics of power distribution grids. To optimize the process of allocating on-chip metal resources, inductance/area/resistance tradeoffs in high speed performance distribution grids are explored. Two tradeoff scenarios in power grids with alternating power and ground lines are considered.     

Methodology for Efficient Substrate Noise Analysis in Large-Scale Mixed-Signal Circuits

A methodology is proposed to efficiently analyze substrate noise coupled to a sensitive block due to an aggressor digital block in large-scale mixed-signal circuits. The methodology is based on identifying voltage domains on the substrate by exploiting the small spatial voltage differences on the ground distribution network of the aggressor circuit. Specifically, similarly biased regions on the substrate short-circuited by the ground network are determined, and each of these regions is represented by a single equivalent input port to the substrate. The remaining ports within that domain are ignored to reduce the computational complexity of the extraction process. An algorithm with linear time complexity is proposed to merge those substrate contacts exhibiting a voltage difference smaller than a specified value, identifying a voltage domain. An equivalent contact is placed at the geometric mean of the merged contacts, ignoring all of the remaining ports such as the source/drain junctions of the devices. The ground network impedance is updated for each merged contact based on the proposed algorithm to maintain sufficient accuracy of the noise voltage. The substrate with reduced input ports is extracted using an existing extraction tool to analyze the noise at the sense node. As compared to the full extraction of an aggressor circuit, the methodology achieves a reduction of more than four orders of magnitude in the number of extracted substrate resistors with a peak-to-peak error of 24%.     

Toward a systematic design methodology for large multigigahertzrapid single flux quantum circuits

Rapid single flux quantum (RSFQ) digital circuits have reached the level of medium- to large-scale of integration. At this level, existing design methodologies, developed specifically for RSFQ circuits, have become computationally inefficient. Applying mature semiconductor methodologies to the design of RSFQ circuits, one encounters substantial difficulties originating from the differences between both technologies. In this paper, a new design methodology aimed at large-scale RSFQ circuits is proposed. This methodology is based on a semiconductor semicustom design approach. An established design methodology for small-stale RSFQ digital circuits, based on circuit (junction-level) simulation and device parameter optimization, is used for the design of basic RSFQ cells. A library composed of about 20 basic RSFQ cells has been developed based on this approach. A novel design methodology for large-scale circuits, presented in this paper, is based on logic (gate-level) simulation and timing optimization. This methodology has been implemented around the Cadence integrated design environment and used successfully at the University of Rochester for the design of two large-scale digital circuits     

The Effect of Signal Activity on Propagation Delay of CMOS Logic Gates Driving Coupled On-Chip Interconnections

The effect of interconnect coupling capacitances on neighboring CMOS logic gates driving coupled interconnections strongly depends upon signal activity. A transient analysis of two capacitively coupled CMOS logic gates is presented in this paper for different combinations of signal activity. The uncertainty of the effective load capacitance and propagation delay due to signal activity is addressed. Analytical expressions characterizing the output voltage and propagation delay are also presented for different signal activity conditions. The propagation delay based on these analytical expressions is within 3% as compared to SPICE, while the estimated delay neglecting the difference between the load capacitances can exceed 45%. The logic gates should be properly sized to balance the load capacitances in order to minimize any uncertainty in the delay and load. The peak noise voltage on a quiet interconnection determined from the analytical expressions is within 4% of SPICE. The peak noise voltage on a quiet interconnection can be minimized if the effective output conductance of the quiet logic gate driving the interconnect is increased.     

Oversampled data conversion techniques

The most commonly used sigma-delta modulators, their performance and their range of applications are discussed, and their performance is analyzed. Signal processing for analog-to-digital and digital-to-analog converters is discussed     

Domino logic with variable threshold voltage keeper

A variable threshold voltage keeper circuit technique is proposed for simultaneous power reduction and speed enhancement of domino logic circuits. The threshold voltage of a keeper transistor is dynamically modified during circuit operation to reduce contention current without sacrificing noise immunity. The variable threshold voltage keeper circuit technique enhances circuit evaluation speed by up to 60% while reducing power dissipation by 35% as compared to a standard domino (SD) logic circuit. The keeper size can be increased with the proposed technique while preserving the same delay or power characteristics as compared to a SD circuit. The proposed domino logic circuit technique offers 14% higher noise immunity as compared to a SD circuit with the same evaluation delay characteristics. Forward body biasing the keeper transistor is also proposed for improved noise immunity as compared to a SD circuit with the same keeper size. It is shown that by applying forward and reverse body biased keeper circuit techniques, the noise immunity and evaluation speed of domino logic circuits are simultaneously enhanced.     

Exploiting the on-chip inductance in high-speed clock distributionnetworks

On-chip inductance effects can be used to improve the performance of high-speed integrated circuits. Specifically, inductance improves the signal slew rate (the rise time), virtually eliminates short-circuit power consumption and reduces the area of the active devices and repeaters inserted to optimize the performance of long interconnects. These positive effects suggest the development of design strategies that benefit from on-chip inductance. An example of a clock distribution network is presented to illustrate the process in which inductance can be used to improve the performance of high-speed integrated circuits