Phase-separated polydimethylsiloxane as a dielectric surface treatment layer for organic field effect transistors

We suggest a novel method for treating the surfaces of dielectric layers in organic field effect transistors (OFETs). In this method, a blend of poly(9,9-dioctylfluorene-alt-bithiophene) (F8T2) and dimethylsiloxane (DMS) with a curing agent is spin coated onto the surface of a dielectric substrate, silicon oxide (SiO₂), and then thermally cured. X-ray photoelectron spectroscopy, contact angle measurements, and morphology analysis were used to show that the hydrophilic DMS layer is preferentially adsorbed on the SiO₂ substrate during the spin coating process. After thermal curing, the bottom DMS layer becomes a hydrophobic PDMS layer. This bottom PDMS layer becomes thinner during curing due to the upward motion of the hydrophobic PDMS molecules. The FET mobility of the cured system was 10^?2 cm²/Vs, which is similar to that of polymeric semiconductors on octadecyltrichlorosilane treated SiO₂ dielectric layers. We also discuss the possibility of using this blend method to increase the air-stability of polymeric semiconductors.     

A low‐complexity single‐carrier frequency‐division multiple access transmitter

A framework for a computationally efficient single‐carrier frequency‐division multiple access (SC‐FDMA) transmitter is proposed in this paper. Compared with a wide system bandwidth, the uplink allocation for each user is supposed to be relatively small because of multiple user access, which makes each user's signal vector to be sparse. When the localized subcarrier allocation is used for SC‐FDMA, the inverse fast fourier transform can take advantage of the sparse user input vector to reduce its complexity. The analytical and simulation results show that the proposed framework can provide a significant complexity reduction compared with the conventional SC‐FDMA transmitter. Copyright © 2011 John Wiley & Sons, Ltd.     

Design and Analysis of Optimal Multi-Level Hierarchical Mobile IPv6 Networks

Hierarchical Mobile IPv6 (HMIPv6) is an enhanced version of Mobile IPv6 designed to reduce signaling overhead and to support seamless handoff in IP-based wireless/mobile networks. To support more scalable services, HMIPv6 networks can be organized as the form of a multi-level hierarchy architecture (i.e., tree structure). However, since multi-level HMIPv6 networks incur additional packet processing overhead at multiple mobility agents, it is important to find the optimal hierarchy level to minimize the total cost, which consists of the location update cost and the packet delivery cost. In this paper, we investigate this problem, namely the design of an optimal multi-level HMIPv6 (OM-HMIPv6) network. To accomplish this, we design a function to represent the location update cost and the packet delivery cost in multi-level HMIPv6 networks. Based on these formulated cost functions, we calculate the optimal hierarchy level in multi-level HMIPv6 networks, in order to minimize the total cost. In addition, we investigate the effects of the session-to-mobility ratio (SMR) on the total cost and the optimal hierarchy. The numerical results, which show various relationships among the network size, optimal hierarchy, and SMR, can be utilized to design an optimal HMIPv6 network. In addition, the analytical results are validated by comprehensive simulations. Sangheon Pack received his B.S. (2000, magna cum laude) and Ph.D. (2005) degrees from Seoul National University, both in computer engineering. He is a post doctor fellow in the School of Computer Science and Engineering at the Seoul National University, Korea. He is a member of the IEEE and ACM. During 2002–2005, he was a recipient of the Korea Foundation for Advanced Studies (KFAS) Computer Science and Information Technology Scholarship. He has been also a member of Samsung Frontier Membership (SFM) from 1999. He received a student travel grant award for the IFIP Personal Wireless Conference (PWC) 2003. He was a visiting researcher to Fraunhofer FOKUS, German in 2003. His research interests include mobility management, wireless multimedia transmission, and QoS provision issues in the next-generation wireless/mobile networks. Yanghee Choi received B.S. in electronics engineering from Seoul National University, M.S. in electrical engineering from Korea advanced Institute of Science, and Doctor of Engineering in Computer Science from Ecole Nationale Superieure des Telecommunications (ENST) in Paris, in 1975, 1977 and 1984 respectively. Before joining the School of Computer Engineering, Seoul National University in 1991, he has been with Electronics and Telecommunications Research Institute (ETRI) during 1977–1991, where he served as director of Data Communication Section, and Protocol Engineering Center. He was research student at Centre National d'Etude des Telecommunications (CNET), Issy-les-Moulineaux, during 1981–1984. He was also Visiting Scientist to IBM T.J. Watson Research Center for the year 1988–1989. He is now leading the Multimedia Communications Laboratory in Seoul National University. He is also director of Computer Network Research Center in Institute of Computer Technology (ICT). He was editor-in-chief of Korea Information Science Society journals. He was chairman of the Special Interest Group on Information Networking. He has been associate dean of research affairs at Seoul National University. He was president of Open Systems and Internet Association of Korea. His research interest lies in the field of multimedia systems and high-speed networking. Minji Nam received her B.S. and M.S degrees in Computer Science and Engineering from Seoul National University in 2003 and 2005, respectively. From 2005, she has worked on Portable Internet Development Team for Korea Telecom. Her research interests are mobile networks, portable internet technology (IEEE 802.16) and Mobile IPv6.     

A Low-Power Unified Arithmetic Unit for Programmable Handheld 3-D Graphics Systems

A low-power, area-efficient four-way 32-bit multifunction arithmetic unit has been developed for programmable shaders for handheld 3D graphics systems. It adopts the logarithmic number system (LNS) at the arithmetic core for the single-cycle throughput and the small-size low-power unification of various complicated arithmetic operations such as power, logarithm, trigonometric functions, vector-SIMD multiplication, division, square root and vector dot product. 24-region and 16-region piecewise linear logarithmic and antilogarithmic converters are proposed with 0.8% and 0.02% maximum conversion error, respectively. All the supported operations are implemented with less than 6.3% operation error and unified into a single arithmetic platform with maximum four-cycle latency and single-cycle throughput. A 93 K gate test chip is fabricated using one-poly five-metal 0.18-mum CMOS technology. It operates at 210 MHz with maximum power consumption of 15.3 mW at 1.8 V.     

Near‐Optimum Blind Decision Feedback Equalization for ATSC Digital Television Receivers

This paper presents a near‐optimum blind decision feedback equalizer (DFE) for the receivers of Advanced Television Systems Committee (ATSC) digital television. By adopting a modified trellis decoder (MTD) with a trace‐ back depth of 1 for the decision device in the DFE, we obtain a hardware‐efficient, blind DFE approaching the performance of an optimum DFE which has no error propagation. In the MTD, the absolute distance is used rather than the squared Euclidean distance for the computation of the branch metrics. This results in a reduction of the computational complexity over the original trellis decoding scheme. Compared to the conventional slicer, the MTD shows an outstanding performance improvement in decision error probability and is comparable to the original trellis decoder using the Euclidean distance. Reducing error propagation by use of the MTD in the DFE leads to the improvement of convergence performance in terms of convergence speed and residual error. Simulation results show that the proposed blind DFE performs much better than the blind DFE with the slicer, and the difference is prominent at the trellis decoder following the blind DFE.     

Image Independent Driving Power Reduction for High Frame Rate LCD Televisions

In this letter, the constant driving power reduction ratio has been achieved for column drivers regardless of the input image by incorporating a new static power reduction scheme into the previous dynamic power reduction method. The measured power reduction ratio is around 50% for a 120 Hz liquid crystal display panel in such cases of still input video and fallback.     

An iterative FEM for scattering by a 3-D cavity-backed aperture

A finite-element method (FEM)-based hybrid method (or iterative FEM) is successfully applied to a three-dimensional (3-D) scattering problem without the effect of internal resonance. With only a small number of meshes around a 3-D scatterer, this FEM is shown to give an accurate result through several iterative updates of the boundary conditions. To confirm the efficiency of this method, scattering from a 3-D cavity-backed aperture is analyzed and the results obtained are compared with the same obtained by another conventional method     

Effect of External Viscous Load on Head Movement

Quantitative measurements of horizontal head rotation were obtained from normal human subjects intending to make "time optimal" trajectories between targets. By mounting large, lightweight vanes on the head, viscous damping B, up to 15 times normal could be added to the usual mechanical load of the head.     

A single capacitor loop filter phase-locked loop with frequency voltage converter

A novel phase-locked loop that has a loop filter consisting of only one capacitor is designed with a frequency voltage converter (FVC). Simulation and measurement results show that the proposed phase-locked loop (PLL) works stably demonstrating that the FVC works effectively as a resistor. Measurement results of the proposed PLL fabricated in a one-poly six-metal 0.18 μm CMOS process show that the phase noise is ?109 dBc/Hz at 10 MHz offset from 752.7 MHz output frequency.     

Architectural Design Issues in a Clockless 32‐Bit Processor Using an Asynchronous HDL

As technology evolves into the deep submicron level, synchronous circuit designs based on a single global clock have incurred problems in such areas as timing closure and power consumption. An asynchronous circuit design methodology is one of the strong candidates to solve such problems. To verify the feasibility and efficiency of a large‐scale asynchronous circuit, we design a fully clockless 32‐bit processor. We model the processor using an asynchronous HDL and synthesize it using a tool specialized for asynchronous circuits with a top‐down design approach. In this paper, two microarchitectures, basic and enhanced, are explored. The results from a pre‐layout simulation utilizing 0.13‐μm CMOS technology show that the performance and power consumption of the enhanced microarchitecture are respectively improved by 109% and 30% with respect to the basic architecture. Furthermore, the measured power efficiency is about 238 μW/MHz and is comparable to that of a synchronous counterpart.