Dependence of electrical properties on the crystallographic orientation of CBr4-doped GaAs epilayers grown on GaAs substrates by atmospheric pressure metalorganic chemical vapor deposition

Carbon incorporation into GaAs epilayers has been performed by atmospheric pressure metalorganic chemical vapor deposition using CBr4. The electrical properties of CBr₄-doped GaAs epilayers grown on the GaAs substrates with various surface crystallographic orientations between (100) and (111)A were investigated. The electrical properties of the epilayers showed a strong crystallographic orientation dependence. On increasing the surface offset angle, the hole concentration of CBr4-doped GaAs epilayers rapidly decreased with a hump at (311)A. The lower hole concentration at the high offset angle can be explained by its higher desorption rate than that of the (100) surface. This hole concentration dependence on the offset angle was not changed in spite of the growth temperature and the V/III ratio variation given in this work. The above behaviors indicate that the surface kinetics plays an important role in the C incorporation into the non-planar GaAs epilayers.     

Winner-Takes-All Associative Memory: A Hamming Distance Vector Quantizer

We present a design methodology for mapping neuralyinspired algorithms for vector quantization, into VLSI hardware.We describe the building blocks used: memory cells, current conveyors,and translinear circuits. We use the basic building blocks todesign an associative processor for bit-pattern classification;a high-density memory based neuromorphic processor. Operatingin parallel, the single chip system determines the closest match,based on the Hamming distance, between an input bit pattern andmultiple stored bit templates; ties are broken arbitrarily. Energyefficient processing is achieved through a precision-on-demandarchitecture. Scalable storage and processing is achieved througha compact six transistor static RAM cell/ALU circuit. The singlechip system is programmable for template sets of up to 124 bitsper template and can store up to 116 templates (total storagecapacity of 14 Kbits). An additional 604 bits of auxiliary storageis used for pipelining and fault tolerance re-configuration capability.A fully functional 6.8 mm by 6.9 mmchip has been fabricated in a standard single–poly, double–metal2.0µmn–well CMOS process.     

Blocky artefact reduction using an adaptive constrained leastsquares method

A blocky artefact reduction algorithm using the constrained least squares (CLS) approach is described. The authors use a new objective function which effectively constrains the relationship between not only the block boundary pixels but also the inner pixels. By gracefully reducing the visible discontinuities along the block boundaries, the proposed algorithm shows excellent noise reduction performance     

Scheduling algorithm for real-time imprecise computations tominimise maximum weighted errors using the linear programmingmethod

An optimal scheduling algorithm for imprecise systems is presented. The proposed algorithm aims at minimising the maximum weighted errors. A novel property of the algorithm is that the errors are evenly distributed among scheduled tasks. The complexity of the proposed algorithm is O(N³) in the worst case, where N is the number of tasks     

Design of variable loop gains of dual-loop DPLL

An approach to the derivation of variable loop gain sequences of dual-loop digital phase-locked loop (DPLL) is developed based on some modifications of the Kalman filtering formulation. It is shown that optimal loop gain sequences which are independent of measurement noise statistics can be obtained under a deterministic source model. Computer simulation results demonstrate that the adaptive dual-loop DPLL designed by using the proposed method is more robust to noise variations than the adaptive DPLL of Driessen (see ibid., vol.47, p.673-75, 1994)     

Three-state synchronization of distributed sample scramblers in thepresence of errors

In this paper, we consider the behaviors and performances of the three-state-based synchronization mechanisms of DSS in the errored environment. We establish a mathematical model to describe the synchronization mechanisms by employing the sequence space theory, and discuss the behaviors of the two different three-state synchronization schemes-the ITU-T recommended thresholded-counting scheme and the newly proposed windowed-observation scheme. We consider the design guidelines for the synchronization schemes, and finally compare their performances in the cell-based ATM     

Unbiased timing-error estimation in the presence of nonidealinterpolation

We propose a method to eliminate the bias term present in the timing-error estimator employed in digital receivers where the input signal is sampled by a fixed clock which is not synchronized to the transmitter clock. This bias error results from the nonideal interpolation that precedes the timing-error estimator. We show that it can be derived as a function of the previously estimated symbol timings. An unbiased timing-error estimate can then be obtained by subtracting this bias term from the output of the timing-error detector. Simulation results are included to show the performance improvement realizable by employing this method     

Er-doped glass ridge-waveguide amplifiers fabricated with a collimated sputter deposition technique

We report a new fabrication process for Er-doped glass ridge waveguides. The process does not require etching of an Er-doped film in defining the lateral dimension of a waveguide, but involves a liftoff process using polyimide as a sacrificial layer. An Er-doped soda-lime silicate glass film (1.5 /spl mu/m thick) was deposited at 350/spl deg/C using a collimated sputtering technique. Conventional sputtering techniques have been known to be incompatible with a liftoff process. The collimated sputtering, however, allowed us easy liftoff of Er-doped films, and produced well-defined ridges with smooth surface profiles. A 1.7-cm-long waveguide thus fabricated shows a 1.55-/spl mu/m signal enhancement of 15.4 dB with a 980-nm pump power of 40 mW. This enhancement fully compensates for both Er absorption and waveguide losses, and results in a gain of 7.2 dB.     

Hybrid pulse position modulation/ultrashort light pulse code-division multiple-access systems .I. Fundamental analysis

We propose a hybrid pulse position modulation/ultrashort light pulse code-division multiple-access (PPM/ULP-CDMA) system for ultrafast optical communications. The proposed system employs spectral CDMA encoding/decoding and PPM with very short pulse separation. The statistical properties of the encoded ULP are investigated with a general pulse model, and the performance of the proposed PPM/ULP-CDMA system is investigated. It is shown that we can improve upon the performance of other ULP-CDMA systems, such as those using on-off keying, by employing PPM. It is also shown that we can improve the performance of the proposed system by increasing the effective number of chips, by increasing the number of PPM symbols, and by reducing the ULP duration. The performance analysis shows that the aggregate throughput of the proposed PPM/ULP-CDMA system could be over 1 Tb/s.     

A fast full search motion estimation algorithm using sequentialrejection of candidates from hierarchical decision structure

We propose a new as well as fast full search (FS) motion estimation algorithm for video coding. The computational reduction comes from sequential rejection of impossible candidates with derived formula and subblock norms. Our algorithm reduces more the computations than the FS motion estimation algorithms previously developed