Instruction‐Level Power Estimator for Sensor Networks

In sensor networks, analyzing power consumption before actual deployment is crucial for maximizing service lifetime. This paper proposes an instruction‐level power estimator (IPEN) for sensor networks. IPEN is an accurate and fine grain power estimation tool, using an instruction‐level simulator. It is independent of the operating system, so many different kinds of sensor node software can be simulated for estimation. We have developed the power model of a Micaz‐compatible mote. The power consumption of the ATmega128L microcontroller is modeled with the base energy cost and the instruction overheads. The CC2420 communication component and other peripherals are modeled according to their operation states. The energy consumption estimation module profiles peripheral accesses and function calls while an application is running. IPEN has shown excellent power estimation accuracy, with less than 5% estimation error compared to real sensor network implementation. With IPEN's high precision instruction‐level energy prediction, users can accurately estimate a sensor network's energy consumption and achieve fine‐grained optimization of their software.     

Intelligent process analytics for CRM

Many organisations use decision models in their processes such as tables or trees to provide decision support to their operational divisions. For example, in fault management, customer contact centre operators usually use a decision model in the form of prescribed interviews. Based on the answers given by customers, the operator navigates through the decision model to reach an assessment of the problem. In order to achieve customer satisfaction and operational excellence, it is very important to constantly monitor the performance of a decision model not only on an overall level, but also on the level of individual decisions. In this paper we present a configurable business process analytics tool, known as the intelligent Universal Service Management System, that constantly monitors decision data and is capable of optimising the decisions based on high-level business objectives. We explain the various features of the software and show how it can be used to optimise decision processes. We also show how we can easily provide a customised version to monitor the performance of provision processes.     

Design of flexible GF(2/sup m/) elliptic curve cryptography processors

The design of flexible elliptic curve cryptography processors (ECP) is considered in this paper. Novel word-level algorithms and implementations for the underlying GF(2/sup m/) multiplication and squaring arithmetic which enable improved flexibility versus performance tradeoffs, are presented and employed in the design of an efficient flexible ECP architecture; corresponding field-programmable gate-array (FPGA) prototyping results for two different processor word lengths are also included for evaluation.     

Placement for large-scale floating-gate field-programable analog arrays

Modern advances in reconfigurable analog technologies are allowing field-programmable analog arrays (FPAAs) to dramatically grow in size, flexibility, and usefulness. Our goal in this paper is to develop the first placement algorithm for large-scale floating-gate-based FPAAs with a focus on the minimization of the parasitic effects on interconnects under various device-related constraints. Our FPAA clustering algorithm first groups analog components into a set of clusters so that the total number of routing switches used is minimized and all IO paths are balanced in terms of routing switches used. Our FPAA placement algorithm then maps each cluster to a computational analog block (CAB) of the target FPAA while focusing on routing switch usage and balance again. Experimental results demonstrate the effectiveness of our approach.     

High‐Performance Dual‐Circularly Polarized Reflector Antenna Feed

This paper presents a high‐performance dual‐circularly polarized feed employing a dielectric‐filled circular waveguide. Novel features are incorporated in the proposed feed, such as a dielectric rod radiator for high gain and good impedance matching; dual quarter‐wave chokes for low axial ratio over wide angles and for low back radiation; an integrated septum polarizer; and two end‐launch‐type coaxial‐to‐waveguide transitions. The proposed feed shows excellent performance at 5.0 GHz to 5.2 GHz.     

Performance study of close-loop power control algorithms for acellular CDMA system

Performance of a reverse link code-division multiple-access (CDMA) system with fast close-loop power control algorithms is studied. It is found that if the fast close-loop power control algorithm functions effectively, the speed of the mobile unit is in the range such that its Doppler frequency is less than one tenth of the power control updating rate. This paper also proposes a new predictive power control algorithm with better performance in terms of system capacity than the conventional and adaptive step size algorithms. An increase in system capacity as high as 22% compared with the conventional algorithm can be achieved depending on the mobile velocity     

Combined beamforming with space-time block coding using double antenna array group

The performance of the combined beamforming of space-time block coding according to the number of antenna array groups has been analysed. CB/spl I.bar/STBC/spl I.bar/single array and CB/spl I.bar/STBC/spl I.bar/double array were compared under the condition of DOA and SNR. CB/spl I.bar/STBC/spl I.bar/double array is shown to have a stable performance independent of DOA and angular spread.     

Highly Efficient Video Codec for Entertainment‐Quality

We present a novel video codec for supporting entertainment‐quality video. It has new coding tools such as an intra prediction with offset, integer sine transform, and enhanced block‐based adaptive loop filter. These tools are used adaptively in the processing of intra prediction, transform, and loop filtering. In our experiments, the proposed codec achieved an average reduction of 13.35% in BD‐rate relative to H.264/AVC for 720p sequences.     

A flip-chip packaged 80-nm In0.7Ga0.3As MHEMT for millimeter-wave low-noise applications

In this paper, we present a flip-chip 80-nm In_0.7Ga_0.3As MHEMT device on an alumina (Al₂O₃) substrate with very little decay on device RF performance up to 60 GHz. After package, the device exhibited high I_DS = 435 mA/mm at V_DS = 1.5 V, high g_m = 930 mS/mm at V_DS = 1.3 V, the measured gain was 7.5 dB and the minimum noise figure (NF_min) was 2.5 dB at 60 GHz. As compared to the bare chip, the packaged device exhibited very small degradation in performance. The result shows that with proper design of the matching circuits and packaging materials, the flip-chip technology can be used for discrete low noise FET package up to millimeter-wave range.