Low-Delay Parallel Architecture for Fractal Image Compression

This paper presents an efficient hardware architecture for implementing fractal image compression (FIC) algorithm aimed toward image compression with improved encoding speed. The proposed architecture follows the full-search-based FIC scheme. Parallel processing has been effectively used in the present work to achieve the goal of reducing the time complexity of the encoder. This architecture requires a total of \(2n+2\) clock cycles for executing the set of operations consisting of fetching the pixels, calculating the mean of range and domain blocks and doing their mapping, computing the error, and storing the fractal parameter in a memory with n number of pixels in the range block. Further, this architecture does not make use of any preprocessing operations as specified in literature and utilizes the benefits of isometric transformation without requiring additional cycles for every single matching operation. Effective application of isometric transformation has also led to memory reduction of nearly 67 %. Again, in the present work, the use of multipliers has been avoided to save the chip area, to reduce hardware complexity, and to enhance the encoding speed. The operation of transforming contracted domain block with a zero-mean domain block has facilitated relatively fast convergence at the decoder. PSNR above 30dB for a range block of size \(4\times 4\) has been achieved by the proposed architecture, which is comparable to that realizable by other architectures. The proposed design has been coded in Verilog HDL, has been implemented in Xilinx Virtex-5 FPGA, and operates at a clock frequency of 75.52 MHz.     

Adaptive Threshold Detection and Estimation of Linear Frequency-Modulated Continuous-Wave Signals Based on Periodic Fractional Fourier Transform

The fractional Fourier transform (FRFT) has been used to detect and estimate the parameters of linear frequency-modulated continuous-wave (LFMCW) in low probability of intercept radar waveforms. The FRFT, which is optimal for single linear frequency-modulated (LFM) signals, becomes sub-optimal when applied to LFMCW signals because the observed waveform of this type of signal is composed of concatenated LFM pulses. A new signal processing method, called the periodic FRFT (PFRFT), is proposed for the detection of LFMCW signals. First, the discrete PFRFT is studied and the signal processing gain of this transform for LFMCW signals is analyzed. Second, an adaptive threshold detection and estimation algorithm for LFMCW signals is formulated after analysis of the test statistics of the squared modulus of LFMCW signals when using the probability density function in the presence of Gaussian white noise. It is then proved that PFRFT-based estimation is equivalent to maximum likelihood estimation in the detection and estimation of LFMCW signals. Finally, the results of both the theoretical analysis and verification simulations show that the PFRFT significantly outperforms the FRFT for LFMCW signals.     

Second-Order Consensus of Multi-agent Systems via Periodically Intermittent Pinning Control

In this paper, we investigate the leader-following consensus of second-order multi-agent systems with nonlinear dynamics and time delay by employing periodically intermittent pinning control. All member agents and the virtual leader share the same nonlinear dynamics relating to the velocity and delayed velocity information. Based on Lyapunov stability theory, we obtain a novel criterion that is independent of the time delay and control width to guarantee the second-order consensus of multi-agent systems with time delay and periodically intermittent controllers. Numerical simulations are presented to illustrate the theoretical results.     

Low Voltage High Output Impedance Bulk-Driven Quasi-Floating Gate Self-Biased High-Swing Cascode Current Mirror

A low voltage self-biased high-swing cascode current mirror using bulk-driven quasi-floating gate MOSFET is proposed in this paper. The proposed current mirror bandwidth and especially the output impedance show a significant improvement compared to prior arts. The current mirror presented is designed using bulk-driven and bulk-driven quasi-floating gate N-channel MOS transistors, which helped it to operate at very low supply voltage of \({\pm }0.2\,\hbox {V}\). To achieve high output resistance, the current mirror uses regulated cascode stage followed by super cascode architecture. The small-signal analysis carried out proves the improvement achieved by proposed current mirror. The current mirror circuit operates well for input current ranging from 0 to \(250\,{\upmu }\mathrm{A}\) with good linearity and shows the bandwidth of 285 MHz. The input and output resistances are found as \(240\,\Omega \) and \(19.5\,\hbox {G}\Omega \), respectively. Further, the THD analysis and Monte Carlo simulations carried prove the robustness of proposed current mirror. The complete analysis is done using HSpice on UMC \(0.18\,\upmu \mathrm{m}\) technology.     

Unfalsified Adaptive PID Control for Time-Varying Systems Using a Fading Memory Cost Function

In this paper, we present a new cost function based on fading memory and time-window in order to decrease the influence of old data in unfalsified adaptive control applications, where the plant varies slowly or changes suddenly with time. Based on the unfalsified adaptive PID control, and the linear increasing cost-level algorithm (LICLA) switching algorithm, the new cost function can guarantee that the switching will stop and the system is stable. A systematic analysis of the system stabilization has been given. The simulation results show that without any prior knowledge of the system plant, when the current controller inserted in the system cannot guarantee the stability of the system, the cost function with a fading memory can detect the instability more quickly and then switch into a new stabilizing controller faster than the original cost function.     

Design and Performance Study of Dynamic Fractors in Any of the Four Quadrants

A fractor is a simple fractional-order system. Its transfer function is \(1/Fs^{\alpha }\); the coefficient, F, is called the fractance, and \(\alpha \) is called the exponent of the fractor. This paper presents how a fractor can be realized, using RC ladder circuit, meeting the predefined specifications on both F and \(\alpha \). Besides, commonly reported fractors have \(\alpha \) between 0 and 1. So, their constant phase angles (CPA) are always restricted between \(0^{\circ }\) and \(-90^{\circ }\). This work has employed GIC topology to realize fractors from any of the four quadrants, which means fractors with \(\alpha \) between \(-\)2 and +2. Hence, one can achieve any desired CPA between \(+180^{\circ }\) and \(-180^{\circ }\). The paper also exhibits how these GIC parameters can be used to tune the fractance of emulated fractors in real time, thus realizing dynamic fractors. In this work, a number of fractors are developed as per proposed technique, their impedance characteristics are studied, and fractance values are tuned experimentally.     

Robust Stability and $$H_{\infty }$$ Control of Discrete-Time Uncertain Impulsive Systems with Time-Varying Delay

This paper considers the robust stability and \(H_{\infty }\) control problems for a class of discrete-time uncertain impulsive systems with time-varying delay. Sufficient conditions for the robust stability, stabilization and \(H_\infty \) control of the considered systems are developed. Some numerical examples are presented to show the effectiveness of the theoretical results.     

Three-Dimensional Chaotic Autonomous System with a Circular Equilibrium: Analysis,Circuit Implementation and Its Fractional-Order Form

A three-dimensional autonomous chaotic system with a circular equilibrium is investigated in this paper. Some dynamical properties and behaviors of this system are described in terms of equilibria, eigenvalue structures, bifurcation diagrams, Lyapunov exponents, time series and phase portraits. For specific parameters, the system displays periodic and chaotic attractors. The physical existence of the chaotic behavior found in the proposed system is verified by using the Orcad-PSpice software and experimental verification. A good qualitative agreement is shown between the experimental results, PSpice and numerical simulations. Furthermore, the commensurate fractional-order version of the system with a circular equilibrium is numerically studied. It is found that chaos exists in this system with order less than three. By tuning the commensurate fractional order, the system with a circular equilibrium displays chaotic and periodic attractors, respectively. Finally, chaos synchronization of identical fractional-order chaotic systems with a circular equilibrium is achieved by using the unidirectional linear error feedback coupling. It is shown that the fractional-order chaotic system can achieve synchronization for appropriate coupling strength.     

An Improved-Linearity,Single-Stage Variable-Gain Amplifier Using Current Squarer for Wider Gain Range

A novel single-stage variable-gain amplifier (VGA) based on transconductance \(g_{m}\)-ratio amplifier is analyzed and designed with wider linear-in-dB gain range and improved linearity. The variable-gain amplifier proposed here consists of an exponential control block, a current squarer and an amplifier block with both input and load degeneration. With the help of current squarer which gets square function of the output current from exponential control block, the VGA achieves the maximum linear gain range in single stage. Current squarer is proposed, which is designed with compensation technique to minimize the second-order effect caused by carrier mobility reduction in short channel MOSFET. To avoid the poor linearity performance of the \(g_{{m}}\)-ratio amplifiers, the distortion is analyzed and the linearity is improved by applying input and load degenerating technique. At the same power consumption, the input 1 dB compression point can be improved by nearly 8.78 dB. Simulation results show that the VGA can provide a gain variation range of 64.09 dB (from \(-35.59\) to 28.5 dB) with a 3-dB bandwidth from 47 to 640 MHz. The circuit consumes the maximum power 3.5 mW from a 1.8-V supply.