Fabrication method for IC-oriented Si single-electron transistors

A new fabrication method for Si single-electron transistors (SETs) is proposed. The method applies thermal oxidation to a Si wire with a fine trench across it on a silicon-on-insulator substrate. During the oxidation, the Si wire with the fine trench is converted, in a self-organized manner, into a twin SET structure with two single-electron islands, one along each edge of the trench, due to position-dependent oxidation-rate modulation caused by stress accumulation. Test devices demonstrated, at 40 K, that the twin SET structure can operate as two individual SET's. Since the present method produces two SET's at the same time in a tiny area, it is suitable for integrating logic circuits based on pass-transistor type logic and CMOS-type logic, which promises to lead to the fabrication of single-electron logic LSIs     

Influence of Diffused Boron Into MgO Barrier on Pinhole Creation in CoFeB/MgO/CoFeB Magnetic Tunnel Junctions

A relationship between boron (B) diffusion into the MgO barrier and pinhole creation in CoFeB/MgO/CoFeB-magnetic tunnel junctions (MTJs) was investigated. The diffused B in the MgO layer was identified by secondary ion mass spectrometry for the MTJs annealed at 350degC , which provide the giant magnetoresistance (TMR) ratio. The pinhole density, estimated from the statistic distribution of breakdown voltage of the TMR properties, increased as either the thickness or the B content of the CoFeB layer became thicker or higher. These experimental findings imply that the diffused B into the MgO barrier creates pinholes to short-circuit the tunnel conduction, since the amount of diffused B into the MgO barrier might be related to the total amount of the B content in the CoFeB layer. Three different techniques were found to be useful for the reduction of diffused B into the MgO barrier layer; usage of materials having boron affinity for capping layer, decrease of the total amount of B-content in CoFeB layer, and reduction of grain boundaries in the MgO barrier layer.     

The structures and gas-sorption properties of l-tyrosine films prepared by the Knudsen effusion method

l-tyrosine (L-Tyr) films with an oblique columnar structure were prepared by the Knudsen cell effusion method. The L-Tyr films were formed at a Knudsen cell temperature that was sufficiently lower than the decomposition temperature of L-Tyr. As the heating rate controlled by DC current is increased, the molecular network constructed of hydrogen bonds tends to collapse, and the film density and surface hydrophobicity tend to decrease. Higher DC currents are likely to induce a decarboxylation reaction. L-Tyr films prepared at a higher heating rate have enhanced gas sorption capabilities for a wide range of volatile organic compounds (VOCs). The sorption capabilities are particularly enhanced for linear hydrocarbons. The gas sorption characteristics for VOCs suggest that the adsorption in the vicinity of the film surface is dominant rather than diffusion into the film, which corresponds with the densified surface morphology.     

Enhanced CaMKII activity and spatial cognitive function in SAMP6 mice.

Senescence-accelerated mouse prone 6 (SAMP6) mice exhibit increased expression of NMDA receptor NR2B subunit (NR2B) and improved short-term memory compared with senescence-accelerated mouse resistance 1 (SAMR1) mice. The Thr286 phosphorylation of alpha calcium/calmodulin-dependent protein kinase II (CaMKII) has a crucial role in plasticity and learning among multiple downstream signaling pathways linked to the NMDA receptor. To examine the relationship between CaMKII activity and spatial learning in SAMP6, the authors employed western blot analysis and behavioral analyses (object location and delayed spatial win-shift eight-arm radial-maze tests). The levels of Thr286 and Ser831 phosphorylation of CaMKII and AMPA receptor subunit glutamate receptor 1 (CaMKII substrate), respectively, were increased in hippocampus of SAMP6 compared with SAMR1. SAMP6 showed faster hippocampal-dependent spatial memory formation than SAMR1 in both the object location and win-shift eight-arm radial-maze tests. Our results indicate that increased CaMKII activity influences the NR2B/CaMKII signal pathway and cognitive function in SAMP6. (PsycINFO Database Record (c) 2010 APA, all rights reserved)     

Production technology of large-area multicrystalline silicon solar cells

In 1996 a conversion efficiency of 17.1% had been obtained on 15 cm×15 cm mc-Si solar cell. In this paper, large-scale production technology of the high-efficiency processing will be discussed. Enlarging reactive ion etching (RIE) equipment size, technology of passivation, and fine contact grid with low resistance by screenprinted metallization, which is firing through PECVD SiN, have been investigated.     

A multigigabit DRAM technology with 6F2 open-bitlinecell, distributed overdriven sensing, and stacked-flash fuse

A multigigabit DRAM technology was developed that features a low-noise 6F² open-bitline cell with fully utilized edge arrays, distributed overdriven sensing for operation below 1 V, and a highly reliable post-packaging repair scheme using a stacked-flash fuse. This technology, which can be used to fabricate a 0,13-μm 180-mm² 1-Gb DRAM assembled in a 400-mil package, was verified using a 57.6-mm², 200-MHz array-cycle, 256-Mb test chip with 0.109-μm² cells     

A 1.0-V 230-MHz column access embedded DRAM for portable MPEGapplications

This paper describes a 32-Mb embedded DRAM macro fabricated using 0.13-μm triple-well 4-level Cu embedded DRAM technology, which is suitable for portable equipment of MPEG applications. This macro can operate 230-MHz random column access even at 1.0-V power supply condition. The peak power consumption is suppressed to 198 mW in burst operation. The power-down standby mode, which suppresses the leakage current consumption of peripheral circuitry, is also prepared for portable equipment. With the collaboration of array circuit design and the fine Cu metallization technology, macro size of 18.9 mm² and cell efficiency of 51.3% are realized even with dual interface and triple test functions implemented