Mobility Enhancement Technology for Scaling of CMOS Devices: Overview and Status

The aggressive downscaling of complementary metal–oxide–semiconductor (CMOS) technology to the sub-21-nm technology node is facing great challenges. Innovative technologies such as metal gate/high-k dielectric integration, source/drain engineering, mobility enhancement technology, new device architectures, and enhanced quasiballistic transport channels serve as possible solutions for nanoscaled CMOS. Among them, mobility enhancement technology is one of the most promising solutions for improving device performance. Technologies such as global and process-induced strain technology, hybrid-orientation channels, and new high-mobility channels are thoroughly discussed from the perspective of technological innovation and achievement. Uniaxial strain is superior to biaxial strain in extending metal–oxide–semiconductor field-effect transistor (MOSFET) scaling for various reasons. Typical uniaxial technologies, such as embedded or raised SiGe or SiC source/drains, Ge pre-amorphization source/drain extension technology, the stress memorization technique (SMT), and tensile or comprehensive capping layers, stress liners, and contact etch-stop layers (CESLs) are discussed in detail. The initial integration of these technologies and the associated reliability issues are also addressed. The hybrid-orientation channel is challenging due to the complicated process flow and the generation of defects. Applying new high-mobility channels is an attractive method for increasing carrier mobility; however, it is also challenging due to the introduction of new material systems. New processes with new substrates either based on hybrid orientation or composed of group III–V semiconductors must be simplified, and costs should be reduced. Different mobility enhancement technologies will have to be combined to boost device performance, but they must be compatible with each other. The high mobility offered by mobility enhancement technologies makes these technologies promising and an active area of device research down to the 21-nm technology node and beyond.     

Use of flip ambiguity probabilities in robust sensor network localization

Collinear or near collinear placement of some sensors in a wireless sensor network causes the location estimates of nearby sensors to be sensitive to erroneous distance measurements which leads to large location estimation errors. These errors and the possible propagation of these errors to the entire network or a large portion of it, thereby causing larger estimation errors for some sensors’ locations, is a major problem in localization. This phenomenon is well described in rigid graph theory, using the notion of “flip ambiguity”. This paper considers arbitrary sensor neighborhoods of two dimensional sensor networks and formulates an analytical expression for the probability of occurrence of the flip ambiguity. Based on the derived probability expression, a methodology is proposed to make the localization algorithms robust by calculating such flip ambiguity probabilities and eliminating potentially poor location estimates as well as assigning confidence factors to the estimated locations to prevent them from ruining the subsequent localization steps. The efficiency of the proposed methodology is demonstrated via a set of simulations.     

RFID Transponder Collision Control Algorithm

Transponder collision problem can be significant when a large number of RFID (radio frequency identification) transponders exist in field. Most existing anti-collision algorithms can solve this problem. However, problem arises when all or part of these transponders are having identical UID (unique identification). This paper proposes a new transponder collision control algorithm to overcome overlapping that occurs among transponders with identical UID in RFID large scale deployment (e.g., in a large warehouse), so that the RFID reader can successfully identify the quantity of transponders for each particular UID with high identification accuracy. The proposed anti-collision algorithm adopts a modified version of frequency domain method by adding stochastic delays in time domain. The obtained results show that the proposed method can achieve optimum frequency bandwidth utilization and at the same time poses high identification accuracy (almost 100%) with low identification delay.     

Design Methodology for Offloading Software Executions to FPGA

Field programmable gate array (FPGA) is a flexible solution for offloading part of the computations from a processor. In particular, it can be used to accelerate an execution of a computationally heavy part of the software application, e.g., in DSP, where small kernels are repeated often. Since an application code for a processor is a software, a design methodology is needed to convert the code into a hardware implementation, applicable to the FPGA. In this paper, we propose a design method, which uses the Transport Triggered Architecture (TTA) processor template and the TTA-based Co-design Environment toolset to automate the design process. With software as a starting point, we generate a RTL implementation of an application-specific TTA processor together with the hardware/software interfaces required to offload computations from the system main processor. To exemplify how the integration of the customized TTA with a new platform could look like, we describe a process of developing required interfaces from a scratch. Finally, we present how to take advantage of the scalability of the TTA processor to target platform and application-specific requirements.     

Adaptive Modeling of Analog/RF Circuits for Efficient Fault Response Evaluation

In this paper, we propose a methodology for adaptive modeling of analog/RF circuits. This modeling technique is specifically geared towards evaluating the response of a faulty circuit in terms of its specifications and/or measurements. The goal of this modeling approach is to compute important test metrics, such as fail probability, fault coverage, and/or yield coverage of a given measurement under process variations. Once the models for the faulty and fault-free circuit are generated, we can simply use Monte-Carlo sampling (as opposed to Monte-Carlo simulations) to compute these statistical parameters with high accuracy. We use the error budget that is defined in terms of computing the statistical metrics and the position of the threshold(s) to decide how precisely we need to extract the necessary models. Experiments on LNA and Mixer confirm that the proposed techniques can reduce the number of necessary simulations by factor of 7 respectively, in the computation of the fail probability.     

Photoluminescence and Raman Spectroscopy of Polycrystalline ZnO Nanofibers Deposited by Electrospinning

The technique of electrospinning offers the advantage of growing nanowires in bulk quantities in comparison with traditional methods. We report optical studies of polycrystalline zinc oxide (ZnO) nanofibers (∼100 nm thick and 5 μm long) deposited by electrospinning. Photoluminescence from the nanofibers shows a near-ultraviolet (near-UV) peak corresponding to near-band-edge emission and a strong broad peak in the visible region from oxygen antisite and interstitial defects. Temperature-dependent photoluminescence spectroscopy reveals that different carrier recombination mechanisms are dominant at low temperature. Our Raman spectroscopy results demonstrate that characterization of the quasimodes of longitudinal optical (LO) and transverse optical (TO) phonons present in an ensemble of polycrystalline nanofibers tilted at various angles in addition to the dominant E ₂(high) mode provides a promising technique for assessing the quality of such randomly oriented nanowires.     

RAI: A High Throughput Routing Protocol for Multi-hop Multi-rate Ad hoc Networks

The advantages of using the multiple rates for wireless communications have been revealed in the recent years. To determine the appropriate rate and to make routing decision more precise, the communication nodes need the information from lower layer. Therefore, in this paper, a high throughput routing protocol using lower layer information for Multi-rate Ad-hoc Networks is proposed. We introduce a new routing metric named “Route Assessment Index” (RAI). The route with maximum RAI value is preferred to achieve the high throughput route, and to avoid the link bottleneck for reducing the packet drop rate. The chosen route also has a small number of hops. The routing protocol works in distributed manner, and correctness of the proposal is proven. The simulation results show that our new metric provides an accurate and efficient method for assessing and selecting the best route in Multi-rate Ad-hoc Networks.     

A Behavioral Model of MEMS Convective Accelerometers for the Evaluation of Design and Calibration Strategies at System Level

This paper presents a behavioral model that can be used to improve the manufacturability of systems based on MEMS convective sensors. This model permits to handle faults related to process scattering, taking into account not only the electrical and lateral geometrical parameters but also the influence of the cavity depth. Moreover correlations between conductive and convective phenomena are included. The model is validated with respect to FEM simulations and a very good agreement is obtained between the behavioral model and FEM results. The proposed model can then be used in system-level simulations, for instance to evaluate the impact of process scattering on the performances of the sensing part and/or to investigate different design and calibration strategies with respect to the system robustness.     

Computing the Detection Probability for Small Delay Defects of Nanometer ICs

Interconnect imperfections have become an important issue in modern nanometer technologies. Some of them cause Small Delay Defects (SDDs) which are difficult to detect. Those SDDs not detected during testing may pose a reliability problem. Furthermore, nanometer issues (e.g. process variations, spatial correlations) represent important challenges for traditional delay test methods. In this paper, a methodology to compute the Detection Probability (DP) of resistive open and bridge defects using a statistical timing framework that takes into account process variations and other nanometer issues is proposed. The DP gives the sensitivity of the circuit performance to a given resistance range of the defect. The efficiency issue when analyzing large circuits is alleviated using stratified sampling techniques to reduce the space of possible analyzed defect locations This methodology is applied to some ISCAS benchmark circuits. The obtained results show the feasibility of the proposed methodology. Measures can be taken for those circuits presenting non-acceptable DP in order to improve the test quality.     

Studies on Conducting Polypyrrole/Graphene Oxide Composites as Supercapacitor Electrode

An electrode material based on polypyrrole (PPy) doped with graphene oxide (GO) sheets was synthesized via in situ polymerization of pyrrole in the presence of GO in various proportions (5% and 10%). The synthesized samples were characterized by Fourier-transform infrared (FTIR) spectroscopy, ultraviolet–visible (UV–vis) absorption spectroscopy, scanning electron microscopy (SEM), transmission electron microscopy (TEM), thermogravimetric analysis (TGA), x-ray diffraction (XRD) analysis, and electrical conductivity measurements. FTIR spectroscopy and XRD revealed the interaction between GO and PPy. The direct-current (DC) electrical conductivity (75.8 S/cm) of the prepared composites was dramatically enhanced compared with pure PPy (1.18 S/cm). High specific capacitance of PPy/GO composite of 421.4 F/g was obtained in the potential range from 0 V to 0.50 V at 2 mA compared with 237.2 F/g for pure PPy by galvanostatic charge–discharge analysis. Incorporation of GO into the PPy matrix has a pronounced effect on the electrical conductivity and electrochemical capacitance performance of PPy/GO nanocomposites.