A Topological Implementation for Motion Planning of a Robotic Arm

An efficient path planning algorithm based on topologic method is presented in this paper.The collision free path planning for three-joint robotic arm consists of three parts:partition of C-space,construction of CN and search for a path in CN.We mainly solved the problems of partitioning the C-space and undging the connectivity between connected blocks,etc.For the motion planning of a robotic arm with a gripper,we developed the concepts of global planning and local planning,and discussed the basic factors for constructing the planning system.In the paper,some evaluation and analysis of the complexity and reliability of the algorithm are given,together with some ideas to improve the efficiency and increase the reliability.At last,some experimental results are pesented to show the efficency and accuracy of the algorithm.     

废钢铁代用品

优质钢材的冶炼和高水平操作指标的获得需要优良的原料作保证。直接还原铁，碳化铁和脱碳粒铁作为废钢铁代用品，已显示出其价格和品质上的优越性，并弥补了废铁数量的不足，但因其各有自身的特点，故研究其理化性质和使用性能，将为大规模生产和使用创造必要的条件。     

醇镁还原法一步制取对氯苯胺的研究

醇镁还原法一步制取对氯苯胺是一种新的方法 ,研究发现最佳反应温度为 80℃～ 85℃ ,反应时间为4h ,对氯硝基苯与镁粉的用量 (物质的量比 )为 1∶3,产率为 80 %。     

Measurements of single chain form factors by small-angle neutron scattering from polystyrene blends containing high concentrations of labelled molecules

A series of small angle neutron scattering measurements on blends of normal polystyrene (PSH) and labelled (deuterated) polystyrene (PSD) have been made with concentrations of PSD from 5 to 50 mol %. It is shown that the single chain form factor of the polymer in bulk can be obtained from a single concentration measurement for any concentration of labelled molecules, providing the molecular weights of the parent and labelled molecules are the same and the molecular weight distributions are narrow.     

Delay-dependent state estimation for delayed neural networks

In this letter, the delay-dependent state estimation problem for neural networks with time-varying delay is investigated. A delay-dependent criterion is established to estimate the neuron states through available output measurements such that the dynamics of the estimation error is globally exponentially stable. The proposed method is based on the free-weighting matrix approach and is applicable to the case that the derivative of a time-varying delay takes any value. An algorithm is presented to compute the state estimator. Finally, a numerical example is given to demonstrate the effectiveness of this approach and the improvement over existing ones.     

冷媒充填机的PLC控制

介绍了冷媒充填机控制系统的组成和工作原理，着重叙述了西门子S7－200可编程控制器与触摸屏结合的控制方式，使系统的性能得到较大的提高。     

化肥厂合成气及重整氢真空变压吸附制取高纯度氢气

从设计、生产操作和经济效益3个方面阐述了以化肥厂合成气及重氢为原料，通过真空变压吸附（VPSA）装置制取高纯度氢的过程。工业应用结果表明，该制氢工艺是一项操作简便灵活，制氢费用较低的工艺路线。VPSA装置技术和设计上的特点能够保证大的操作弹性、高的产品氢纯度和较高的氢气回收率。在36％－51％的低限负荷下，通过适当调整吸附时间，可获得纯度99％的氢气产品，89％－92％的氢气回收率。     

End-User Computing in a CASE Environment

Computer-aided software engineering (CASE) tools are currently being used by IS professionals rather than by users. No matter how effective these tools may be, however, they will not be able to assist in the reduction of application backlogs without supporting user-driven applications. This article examines characteristics of a CASE environment from the various perspectives of decision support, identifies the advantages and limitations of end-user computing in this environment, and suggests how IS managers can realize the potentials of CASE for user applications.     

A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM

In this paper we propose a novel built-in self-test (BIST) design for embedded SRAM cores. Our contribution includes a compact and efficient BIST circuit with diagnosis support and an automatic diagnostic system. The diagnosis module of our BIST circuit can capture the error syndromes as well as fault locations for the purposes of repair and fault/failure analysis. In addition, our design provides programmability for custom March algorithms with lower hardware cost. The combination of the on-line programming mode and diagnostic system dramatically reduces the effort in design debugging and yield enhancement. We have designed and implemented test chips with our BIST design. Experimental results show that the area overhead of the proposed BIST design is only 2.4% for a 128 KB SRAM, and 0.65% for a 2 MB one.