Catalytic aminolysis of epoxide by alumina prepared from amine-protected Al precursor

The catalytic activities of alumina prepared from an Al alkoxide-amine adduct monomer for the reaction of cyclopentene oxide with piperidine was determined after various pretreatments, including calcination and exposure to moisture. They were compared with the activity of alumina prepared by the conventional hydrolysis method. It was found that the as-prepared sample from the alkoxide-amine monomer preparation was five times more active than a conventional preparation, suggesting that it has a higher density of surface Lewis acid sites. However, its activity was much more severely suppressed by exposure to moisture.     

A decision support system for interactive decision making - Part II: analysis and output interpretation

For pt.I see ibid., p.42-55 (2003). The development of a comprehensive decision support system, GMCR II, for the systematic study of real-world interactive decision problems is presented. The companion paper (Part I), discusses how GMCR II elicits, stores, and manages conflict models; here (Part II), the focus is on GMCR IIs analysis and output interpretation subsystems. Specifically, this paper describes the powerful and efficient analysis engine contained in GMCR II, its informative output presentation and interpretation facilities, and a number of follow-up analyses. Furthermore, an illustrative case study is used to demonstrate how GMCR II can be conveniently applied in practice.     

Control system design on a power-split CVT for high-power agricultural tractors

The problem considered in this paper is the design and tuning of the control system of a power-split continuously variable transmission (CVT) used in high-power tractors. Power-split CVTs are characterized by the combination of a traditional mechanical transmission and by a continuously-variable transmission. This guarantees, at the same time, smooth variations of the transmission-ratio and high efficiency of the overall transmission system. The control architecture of an hydrostatic power-split CVT is constituted by three main parts: 1) servo-controller on the current of the valve which drives the hydraulic transmission; 2) a servo-controller on the hydraulic transmission-ratio; and 3) a synchronizer which coordinates the hydraulic and the mechanical parts of the CVT. In this work, these three controllers are fully developed, including: design, implementation, and evaluation on an experimental system.     

On-demand learning for a wireless campus

The current Internet and wireless networks are harsh environments for transporting high-bandwidth multimedia data. We examine the technical issues involved, and describe an end-to-end solution to support a Web-based learn-on-demand system that operates in a wireless campus environment.     

Practical OSPF traffic engineering

Open Shortest Path First (OSPF) traffic engineering (TE) is intended to bring long-awaited traffic management capabilities into IP networks, which still rely on today's prevailing routing protocols: OSPF or IS-IS. In OSPF, traffic is forwarded along, and split equally between, equal cost shortest paths. In this letter, we formulate the basic requirements placed on a practical TE architecture built on top of OSPF and present a theoretical framework meeting these requirements of practicality. The main contribution of our work comes from the recognition that coupled with an instance of the maximum throughput problem there exists a related inverse shortest-path problem yielding optimal OSPF link weights.     

Techniques for high-frequency integrated test and measurement

This paper describes techniques for the on-chip measurement of high-frequency and/or high-bandwidth electrical phenomena in ultra large-scale integration environments. The techniques rely on the integration of multiple compact and robust electronic test devices, or cores, at various locations within an integrated circuit. The cores consist primarily of signal generators that approximate the output of a sigma-delta modulator using finite repetitious bit patterns and a small set of highly robust analog components. They are capable of digitizing on-chip signals at gigahertz rates even using low-cost manufacturing processes. Simple communication between the multiple cores enables the migration of many "board-level" type measurements down to the chip level.