On loop transformations for generalized cycle shrinking

This paper describes several loop transformation techniques for extracting parallelism from nested loop structures. Nested loops can then be scheduled to run in parallel so that execution time is minimized. One technique is called selective cycle shrinking, and the other is called true dependence cycle shrinking. It is shown how selective shrinking is related to linear scheduling of nested loops and how true dependence shrinking is related to conflict-free mappings of higher dimensional algorithms into lower dimensional processor arrays. Methods are proposed in this paper to find the selective and true dependence shrinkings with minimum total execution time by applying the techniques of finding optimal linear schedules and optimal and conflict-free mappings proposed by W. Shang and A.B. Fortes     

Scheduling DAG's for asynchronous multiprocessor execution

A new approach is given for scheduling a sequential instruction stream for execution “in parallel” on asynchronous multiprocessors. The key idea in our approach is to exploit the fine grained parallelism present in the instruction stream. In this context, schedules are constructed by a careful balancing of execution and communication costs at the level of individual instructions, and their data dependencies. Three methods are used to evaluate our approach. First, several existing methods are extended to the fine grained situation. Our approach is then compared to these methods using both static schedule length analyses, and simulated executions of the scheduled code. In each instance, our method is found to provide significantly shorter schedules. Second, by varying parameters such as the speed of the instruction set, and the speed/parallelism in the interconnection structure, simulation techniques are used to examine the effects of various architectural considerations on the executions of the schedules. These results show that our approach provides significant speedups in a wide-range of situations. Third, schedules produced by our approach are executed on a two-processor Data General shared memory multiprocessor system. These experiments show that there is a strong correlation between our simulation results, and these actual executions, and thereby serve to validate the simulation studies. Together, our results establish that fine grained parallelism can be exploited in a substantial manner when scheduling a sequential instruction stream for execution “in parallel” on asynchronous multiprocessors     

On the performance of synchronized programs in distributed networkswith random processing times and transmission delays

A synchronizer is a compiler that transforms a program designed to run in a synchronous network into a program that runs in an asynchronous network. The behavior of a simple synchronizer, which also represents a basic mechanism for distributed computing and for the analysis of marked graphs, was studied by S. Even and S. Rajsbaum (1990) under the assumption that message transmission delays and processing times are constant. We study the behavior of the simple synchronizer when processing times and transmission delays are random. The main performance measure is the rate of a network, i.e., the average number of computational steps executed by a processor in the network per unit time. We analyze the effect of the topology and the probability distributions of the random variables on the behavior of the network. For random variables with exponential distribution, we provide tight (i.e., attainable) bounds and study the effect of a bottleneck processor on the rate     

On the design of dynamic associative neural memories

We consider the design problem for a class of discrete-time and continuous-time neural networks. We obtain a characterization of all connection weights that store a given set of vectors into the network, that is, each given vector becomes an equilibrium point of the network. We also give sufficient conditions that guarantee the asymptotic stability of these equilibrium points.     

Neural network control of communications systems

Neural networks appear well suited to applications in the control of communications systems for two reasons: adaptivity and high speed. This paper describes application of neural networks to two problems, admission control and switch control, which exploit the adaptivity and speed property, respectively. The admission control problem is the selective admission of a set of calls from a number of inhomogeneous call classes, which may have widely differing characteristics as to their rate and variability of traffic, onto a network. It is usually unknown in advance which combinations of calls can be simultaneously accepted so as to ensure satisfactory performance. The approach adopted is that key network performance parameters are observed while carrying various combinations of calls, and their relationship is learned by a neural network structure. The network model chosen has the ability to interpolate or extrapolate from the past results and the ability to adapt to new and changing conditions. The switch control problem is the service policy used by a switch controller in transmitting packets. In a crossbar switch with input queueing, significant loss of throughput can occur when head-of-line service order is employed. A solution can be based on an algorithm which maximizes throughput. However since this solution is typically required in less than one microsecond, software implementation policy is infeasible. We will carry out an analysis of the benefits of such a policy, describe some existing proposed schemes for its implementation, and propose a further scheme that provides this submicrosecond optimization.     

Robust crossfeed design for hovering rotorcraft

Control law design for rotorcraft fly-by-wire systems normally attempts to decouple the angular responses using fixed-gain crossfeeds. This approach can lead to poor decoupling over the frequency range of pilot inputs and increase the load on the feedback loops. In order to improve the decoupling performance, dynamic crossfeeds should be adopted. Moreover, because of the large changes that occur in the aircraft dynamics due to small changes about the nominal design condition, especially for near-hovering flight, the crossfeed design must be ‘robust’. A new low-order matching method is presented here to design robust crossfeed compensators for multi-input, multi-output (MIMO) systems. The technique minimizes cross-coupling given an anticipated set of parameter variations for the range of flight conditions of concern. Results are presented in this paper of an analysis of the pitch/roll coupling of the UH-60 Black Hawk helicopter in near-hovering flight. A robust crossfeed is designed that shows significant improvement in decoupling perfomance and robustness over the fixed-gain or single point dynamic compensators. The design method and results are presented in an easily used graphical format that lends significant physical insight to the design procedure. This plant precompensation technique is an appropriate preliminary step to the design of robust feedback control laws for rotorcraft.     

MEETING THE IT CHALLENGES OF BUSINESS The Changing Mandate for MBAs

What is the implication for business when information technology (IT) changes in the workplace without a commensurate change in the composition of business programs educating tomorrow's employees? A survey of MBA graduates forms the basis of this article on the IT skills needed in the marketplace.     

UTEC and Ferut: the University of Toronto's computation centre

Although not well known, the University of Toronto had a very early computer-development program and in 1952 was one of the first few institutions with an operable computer in North America. This article describes the university's initial attempt to build the UTEC computer and how it acquired the pioneering Ferut machine