Energy release rates of crack kinking by boundary condition sensitivity analysis

The energy release rate, which is the total derivative of the energy with respect to crack length, is recognized as corresponding to the shape sensitivity analysis with the crack length change represented by the tangential component of design velocity. In this paper the sensitivity formula recently developed for a changing boundary condition has been further extended to cover crack kinking under mixed mode loading. Due to difficulty in defining the velocity field at the corner, the energy release rate at the onset of crack kinking is obtained by extrapolating the energy release rates for finite length kinked cracks. A rectangular plate with a single edge slant crack under uniform tension is taken as a numerical example. The multi-region technique in the numerical implementation of the boundary integral equation is adopted to consider the asymmetry of the problem. Excellent accuracy is observed as compared with reference analytic solutions.     

Hydride Vapor Phase Epitaxy of GaN Thick Films by the Consecutive Deposition Process Using GaCl3

GaN buffer and main layers were grown by the conventional hydride vapor phase epitaxy technique using GaCl₃ consecutively. The deposited buffer layers were investigated by atomic force microscopy and X-ray analysis. To examine the behavior of the buffer layers at main layer growth temperature, heat treatment was conducted at 900°C. Based on the results of the buffer layer study, GaN thick films were grown at 1050°C. Optimum deposition conditions of buffer layer from the buffer and main layer studies generally coincided. On the φ scanning pattern, the GaN films grown on (0001) Al₂O₃ were single-crystalline. Band-edge emission dominated photoluminescence was observed at room temperature.     

Electrical characterization of porous BaTiO3 using impedance spectroscopy in humid condition

The humidity response characteristics of La doped BaTiO₃ with different sintered densities and room temperature electrical conductivities were investigated using complex impedance measurement. The samples with low density and high resistivity showed the large and nearly linear sensitivity to the change of humidity. The impedance spectra of samples, when exposed to high humidity, can exhibit microstructure-related features, even though they do not give rise to a noticeable characteristic change when exposed to low humidity. The observed impedance patterns were dependent upon the density, and hence the oxidation kinetics of BaTiO₃.     

开发PROFIBUS-DP智能从站

简单介绍了PROFIBUS－DP现场总线，同时讨论了利用89C52单片机和PROFIBUS－DP从站芯片SPC3开发PROFIBUS－DP智能从站的软硬件设计方法。     

Background memory area estimation for multidimensional signalprocessing systems

Memory cost is responsible for a large amount of the chip and/or board area of customized video and image processing system realizations. In this paper, we present a novel technique-founded on data-flow analysis which allows one to address the problem of background memory size evaluation for a given nonprocedural algorithm specification, operating on multidimensional signals with affine indexes. Most of the target applications are characterized by a huge number of signals, so a new polyhedral data-flow model operating on groups of scalar signals is proposed. These groups are obtained by a novel analytical partitioning technique, allowing to select a desired granularity, depending on the application complexity. The method incorporates a way to tradeoff memory size with computational and controller complexity     

A PLL clock generator with 5 to 10 MHz of lock range formicroprocessors

A microprocessor clock generator based on an analog phase-locked loop (PLL) is described for deskewing the internal logic control lock to an external system lock. This PLL is fully generated onto a 1.2-million-transistor microprocessor in 0.8-μm CMOS technology without the need for external components. It operates with a lock range from 5 to 110 MHz. The clock skew is less than 0.1 ns, with a peak-to-peak jitter of less than 0.3 ns for a 50-MHz system clock frequency     

刍议小型水电站项目收购风险管理

相对于其他项目的收购风险评估，小型水电站（电站总装机容量5万kW以下）收购有其特殊性。在总结和归纳小型水电站特点的基础上，结合一般项目收购风险评估方法，分析项目收购各个阶段存在的风险和对策。为有收购水电项目意向的企业和个人提供决策依据。图1幅。     

Numerical modeling of near corona wire electrohydrodynamic flow in a wire-plate electrostatic precipitator

Numerical modelling of the flow velocity fields for the near corona wire electrohydrodynamic (EHD) flow was conducted. Solutions of the steady, two-dimensional momentum equations have been computed for a wire-plate type electrostatic precipitator (ESP). The equations were solved in the conservative finite-difference form on a fine uniform rectilinear grid of sufficient resolution to accurately capture the momentum boundary layers. The numerical procedure for the differential equations was used by SIMPLEST algorithm. The CFD code coupled with Poisson's electric field, ion transport equations and the momentum equation with electric body force, was used for the numerical simulation with the Chen-Kim k-epsiv turbulent model. The numerical results show that EHD secondary flow was clearly visible in the downstream regions of the corona wire despite the low Reynolds number for the electrode (Re _cw=12.4). Secondary flow vortices caused by the EHD increases with increasing discharge current or EHD number, hence pressure drop of ESP increases     

Degradation Behaviors of Metal-Induced Laterally Crystallized n-Type Polycrystalline Silicon Thin-Film Transistors Under DC Bias Stresses

Device degradation behaviors of typical-sized n-type metal-induced laterally crystallized polycrystalline silicon thin-film transistors were investigated in detail under two kinds of dc bias stresses: hot-carrier (HC) stress and self-heating (SH) stress. Under HC stress, device degradation is the consequence of HC induced defect generation locally at the drain side. Under a unified model that postulates, the establishment of a potential barrier at the drain side due to carrier transport near trap states, device degradation behavior such as asymmetric on current recovery and threshold voltage degradation can be understood. Under SH stress, a general degradation in subthreshold characteristic was observed. Device degradation is the consequence of deep state generation along the entire channel. Device degradation behaviors were compared in low V_d-stress and in high V_d-stress condition. Defect generation distribution along the channel appears to be different in two cases. In both cases of SH degradation, asymmetric on current recovery was observed. This observation, when in low V_d-stress condition, is tentatively explained by dehydrogenation (hydrogenation) effect at the drain (source) side during stress