Pure CuBi2O4 Photoelectrodes with Increased Stability by Rapid Thermal Processing of Bi2O3/CuO Grown by Pulsed Laser Deposition

A new method for enhancing the charge separation and photo‐electrochemical stability of CuBi₂O₄ photoelectrodes by sequentially depositing Bi₂O₃ and CuO layers on fluorine‐doped tin oxide substrates with pulsed laser deposition (PLD), followed by rapid thermal processing (RTP), resulting in phase‐pure, highly crystalline films after 10 min at 650 °C, is reported. Conventional furnace annealing of similar films for 72 h at 500 °C do not result in phase‐pure CuBi₂O₄. The combined PLD and RTP approach allow excellent control of the Bi:Cu stoichiometry and results in photoelectrodes with superior electronic properties compared to photoelectrodes fabricated through spray pyrolysis. The low photocurrents of the CuBi₂O₄ photocathodes fabricated through PLD/RTP in this study are primarily attributed to their low specific surface area, lack of CuO impurities, and limited, slow charge transport in the undoped films. Bare (without protection layers) CuBi₂O₄ photoelectrodes made with PLD/RTP shows a photocurrent decrease of only 26% after 5 h, which represents the highest stability reported to date for this material. The PLD/RTP fabrication approach offers new possibilities of fabricating complex metal oxides photoelectrodes with a high degree of crystallinity and good electronic properties at higher temperatures than the thermal stability of glass‐based transparent conductive substrates would allow.     

Synthesis of scanning electron microscopy images by high performance computing for the metrology of advanced CMOS processes

Scanning electron microscopy is still the technique of choice for imaging and for in-line measurement of critical dimensions and overlay accuracy in most of the core technology processes. In particular, critical dimension microscopy provides information about design template matching and edge placement errors through links with design having proven beneficial effects on process yield and product reliability. In this paper, the use of high performance computing is demonstrated to simulate linescans and 2D secondary electron images to be used in optical proximity error correction strategies for nanometer scale technologies.     

Assessment of the Analytical Capabilities of Scanning Capacitance and Scanning Spreading Resistance Microscopy Applied to Semiconductor Devices

In this work we compare the performance of Scanning Capacitance Microscopy and Scanning Spreading Resistance Microscopy for the characterization of doping profiles in semiconductor devices. Particular attention is devoted to parameters of paramount importance for the failure analysis and the characterization of silicon devices, like the quantitative one-dimensional profiling accuracy, the electrical junction delineation and the two-dimensional sub-micron imaging capability.     

Electrolyte‐Gated n‐Type Transistors Produced from Aqueous Inks of WS2 Nanosheets

Solution‐processed, low cost thin films of layered semiconductors such as transition metal dichalcogenides (TMDs) are potential candidates for future printed electronics. Here, n‐type electrolyte‐gated transistors (EGTs) based on porous WS₂ nanosheet networks as the semiconductor are demonstrated. The WS₂ nanosheets are liquid phase exfoliated to form aqueous/surfactant stabilized inks, and deposited at low temperatures (T < 120 °C) in ambient atmosphere by airbrushing. No solvent exchange, further additives, or complicated processing steps are required. While the EGTs are primarily n‐type (electron accumulation), some hole transport is also observable. The EGTs show current modulations > 10⁴ with low hysteresis, channel width‐normalized on‐conductances of up to 0.27 µS µm^?1 and estimated electron mobilities around 0.01 cm² V^?1 s^?1. In addition, the WS₂ nanosheet networks exhibit relatively high volumetric capacitance values of 30 F cm^?3. Charge transport within the network depends significantly on the applied lateral electric field and is thermally activated, which supports the notion that hopping between nanosheets is a major limiting factor for these networks and their future application.     

Parasitic modes on printed circuit boards and their effects on EMCand signal integrity

In this paper, parasitic modes, such as slotline, parallel plane, and surface wave (SW) modes, commonly found on printed circuit boards (PCBs) are analyzed and their effects on electromagnetic compatibility (EMC) and signal integrity are discussed. The analysis is based on numerical simulations using the finite difference time domain (FDTD) method which is shown to be very well suited for rigorous modeling of parasitic mode effects. The EMC and signal integrity problems discussed include power loss, crosstalk, ground bounce, and free space radiation. Design guidelines for improved EMC and signal integrity are derived from the results obtained. Comprehensive simulation and characterization of SWs using FDTD is presented for the first time     

Lifetime extrapolation for IGBT modules under realistic operation conditions

In this paper a systematic approach is presented for extrapolating the lifetime due to bond wire lift-off in IGBT modules submitted to cyclic loading. Application profiles of the device are considered, as they are usually encountered in real current converters for railway traction systems. The proposed lifetime prediction scheme is based on the principle of the linear accumulation of the fatigue damage and takes into account the redundancy of the bond wires.     

SCR operation mode of diode strings for ESD protection

Diodes and diode strings in 90 nm and beyond technologies are investigated by measurement and device simulation. After a thorough calibration, the device simulator is utilised to achieve a better understanding and an enhanced device performance of diode strings under static and transient ESD conditions. Thereto, parasitic transistors and a so far neglected parasitic thyristor (SCR) in the diode string are regarded, exploited and optimised.     

Surge arresters for insulation coordination in UHV power systems—related problems and solutions

Surge arresters play an important role in the insulation coordination of ultra high-voltage (UHV) electric power systems. In this contribution the requirements on the surge arresters are discussed in comparison with those in conventional applications, and how surge arrester standards are being changed to cover these special requirements.     

High-Gain Chemically Gated Organic Electrochemical Transistor

Organic electrochemical transistors (OECTs) have exhibited promising performance as transducers and amplifiers of low potentials due to their exceptional transconductance, enabled by the volumetric charging of organic mixed ionic/electronic conductors (OMIECs) employed as the channel material. OECT performance in aqueous electrolytes as well as the OMIECs’ redox activity has spurred a myriad of studies employing OECTs as chemical transducers. However, the OECT's large (potentiometrically derived) transconductance is not fully leveraged in common approaches that directly conduct chemical reactions amperometrically within the OECT electrolyte with direct charge transfer between the analyte and the OMIEC, which results in sub-unity transduction of gate to drain current. Hence, amperometric OECTs do not truly display current gains in the traditional sense, falling short of the expected transistor performance. This study demonstrates an alternative device architecture that separates chemical transduction and amplification processes on two different electrochemical cells. This approach fully utilizes the OECT's large transconductance to achieve current gains of 10³ and current modulations of four orders of magnitude. This transduction mechanism represents a general approach enabling high-gain chemical OECT transducers.