Performance of Object Classification Using Zernike Moment

Moments have been used in all sorts of object classification systems based on image. There are lots of moments studied by many researchers in the area of object classification and one of the most preference moments is the Zernike moment. In this paper, the performance of object classification using the Zernike moment has been explored. The classifier based on neural networks has been used in this study. The results indicate the best performance in identifying the aggregate is at 91.4% with a ten orders of the Zernike moment. This encouraging result has shown that the Zernike moment is a suitable moment to be used as a feature of object classification systems.     

Photonic crystal-based permutation switch for optical networks

We present, for the first time, the design of a low-cross talk scalable permutation switch employing photonic crystal ring resonators in an optical network. Through this novel approach, the transition between different states of the \(2 \times 2\) optical switch, as the basic element, is achieved by applying different operating wavelengths. Subsequently, the shuffling mechanisms in \(3 \times 3\) and \(4 \times 4\) optical networks are realized by controlling the position of photonics crystal ring resonators. Lowest cross talk levels of 6 and 5% are obtained for “bar” and “cross” switching states, respectively.     

Delay constrained throughput optimisation with imperfect CSI using discrete adaptive power

Link adaptation is an effective tool to overcome fading effects in wireless links. However, time-varying adaptive transmission rate leads to queueing delay, and moreover, in practise, imperfect channel state information (CSI) is available for the transmitter to adapt its transmission rate and power. This article aims to consider practical constraints to enhance the link adaptation scheme. We reformulate and optimise buffer delay constrained throughput of a wireless link based on outdated noisy CSI. Discrete power adaptation is proposed, in which a limited number of feedback bits (just the index of transmission power level) is required, while the performance is improved compared to the constant power and is close to continuous adaptive power. A unified scheme is set-up, where constant, discrete or continuous adaptive power transmission is utilised considering average or instantaneous bit error rate constraints based on imperfect CSI. The effectiveness of our designs is evaluated by numerical evaluations.     

Theoretical Prediction of an Antimony-Silicon Monolayer $$(\hbox {penta-Sb}_{2}\hbox {Si})$$: Band Gap Engineering by Strain Effect

In this paper, using a first principles calculation, a two-dimensional structure of silicon-antimony named penta-Sb\(_{2}\)Si is predicted. The structural, kinetic, and thermal stabilities of the predicted monolayer are confirmed by the cohesive energy calculation, phonon dispersion analysis, and first principles molecular dynamic simulation, respectively. The electronic properties investigation shows that the pentagonal Sb\(_{2}\)Si monolayer is a semiconductor with an indirect band gap of about 1.53 eV (2.1 eV) from GGA-PBE (PBE0 hybrid functional) calculations which can be effectively engineered by employing external biaxial compressive and tensile strain. Furthermore, the optical characteristics calculation indicates that the predicted monolayer has considerable optical absorption and reflectivity in the ultraviolet region. The results suggest that a Sb\(_{2}\)Si monolayer has very good potential applications in new nano-optoelectronic devices.     

Radio-over-free space optical space division multiplexing system using 3-core photonic crystal fiber mode group multiplexers

Wireless Networks - Radio over free space optics (Ro-FSO) systems have previously relied on the signal intensity, wavelength and polarization for multiplexing data streams in...     

Integrating IPsec within OpenFlow Architecture for Secure Group Communication

Network securityprotocolssuch as IPsechave been used for many years to ensure robust end-to-end communication and are impor-tant in the context of SDN.Despite the widespread installation of IPsec to date,per-packet protection offered by the protocol isnot very compatible with OpenFlow and flow-like behavior.OpenFlow architecture cannot aggregate IPsec-ESP flows in transportmode or tunnel mode because layer-3 information is encrypted and therefore unreadable.In this paper,we propose using the Secu-rity Parameter Index(SPI)of IPsec within the OpenFlow architecture to identify and direct IPsec flows.Thisenables IPsec to con-form to the packet-based behavior of OpenFlow architecture.In addition,by distinguishing between IPsec flows,the architectureis particularly suited to secure group communication.     

Energy Detector in Ultra Wideband Systems Using Phase Compensation Technique

Energy detectors have the advantage of simple structure and inexpensive price. Due to the low signal to noise ratio (SNR) of the received signal in ultra-wideBand (UWB) system, these desirable advantages can be achieved at the expense of non-trivial performance degradation. This paper presents a phase compensation (PC) technique to improve the performance of energy detector in UWB systems. In PC-UWB, the frequency dependent phase of the system response at the transmitter is extracted and its opposite spectral phase is used as prefilter. Because of Low complexity, cost and energy consumption of energy detectors, PC techniques has extensive potential for future of UWB communication systems. Measurement results show that the use of PC-UWB leads to signal power concentration at the receiver, which reduces the number of RAKE fingers required in coherent detection as well as achieves a higher data rate with less intersymbol interference. However time reversal UWB can achieve secure data transmission, but its performance is worse than PC-UWB. Simulation results show that phase compensation reduces the inter symbol interference impacts. Therefore it is possible to use a simple receiver with insignificant performance degradation. It is also shown that PC-UWB considerably outperforms TR-UWB and has satisfying performance in SNR greater than 13 dB.     

A Novel Design Methodology for High-Performance Programmable Decoder Cores for AA-LDPC Codes

A new parameterized-core-based design methodology targeted for programmable decoders for low-density parity-check (LDPC) codes is proposed. The methodology solves the two major drawbacks of excessive memory overhead and complex on-chip interconnect typical of existing decoder implementations which limit the scalability, degrade the error-correction capability, and restrict the domain of application of LDPC codes. Diverse memory and interconnect optimizations are performed at the code-design, decoding algorithm, decoder architecture, and physical layout levels, with the following features: (1) Architecture-aware (AA)-LDPC code design with embedded structural features that significantly reduce interconnect complexity, (2) faster and memory-efficient turbo-decoding algorithm for LDPC codes, (3) programmable architecture having distributed memory, parallel message processing units, and dynamic/scalable transport networks for routing messages, and (4) a parameterized macro-cell layout library implementing the main components of the architecture with scaling parameters that enable low-level transistor sizing and power-rail scaling for power-delay-area optimization. A 14.3 mm² programmable decoder core for a rate-1/2, length 2048 AA-LDPC code generated using the proposed methodology is presented, which delivers a throughput of 6.4 Gbps at 125 MHz and consumes 787 mW of power.Mohammad M. Mansour received his B.E. degree with distinction in 1996 and his M.S. degree in 1998 all in Computer and Communications Engineering from the American University of Beirut (AUB). In August 2002, he received his M.S. degree in Mathematics from the University of Illinois at Urbana-Champaign (UIUC). Mohammad received his Ph.D. in Electrical Engineering in May 2003 from UIUC. He is currently an Assistant Professor of Electrical Engineering with the ECE department at AUB. From 1998 to 2003, he was a research assistant at the Coordinated Science Laboratory (CSL) at UIUC. In 1997 he was a research assistant at the ECE department at AUB, and in 1996 he was a teaching assistant at the same department. From 1992–1996 he was on the Deans honor list at AUB. He received the Harriri Foundation award twice in 1996 and 1998, the Charli S. Korban award twice in 1996 and 1998, the Makhzoumi Foundation Award in 1998, and the PHI Kappa PHI Honor Society awards in 2000 and 2001. During the summer of 2000, he worked at National Semiconductor Corp., San Francisco, CA, with the wireless research group. His research interests are VLSI architectures and integrated circuit (IC) design for communications and coding theory applications, digital signal processing systems and general purpose computing systems.Naresh R. Shanbhag received the B.Tech from the Indian Institute of Technology, New Delhi, India, in 1988, M.S. from Wright State University and Ph.D. degree from the University of Minnesota, in 1993, all in Electrical Engineering. From July 1993 to August 1995, he worked at AT&T Bell Laboratories at Murray Hill in the Wide-Area Networks Group, where he was responsible of development of VLSI algorithms, architectures and implementation for high-speed data communications applications. In particular, he was the lead chip architect for AT&Ts 51.84 Mb/s transceiver chips over twisted-pair wiring for Asynchronous Transfer Mode (ATM)-LAN and broadband access. Since August 1995, he is with the Department of Electrical and Computer Engineering, and the Coordinated Science Laboratory where he is presently an Associate Professor and Director of the Illinois Center for Integrated Microsystems. At University of Illinois, he founded the VLSI Information Processing Systems (ViPS) Group, whose charter is to explore issues related to low-power, high-performance, and reliable integrated circuit implementations of broadband communications and digital signal processing systems. He has published numerous journal articles/book chapters/conference publications in this area and holds three US patents. He is also a co-author of the research monograph Pipelined Adaptive Digital Filters (Norwell, MA: Kluwer, 1994). Dr. Shanbhag received the 2001 IEEE Transactions Best Paper Award, 1999 Xerox Faculty Research Award, 1999 IEEE Leon K. Kirchmayer Best Paper Award, the 1997 Distinguished Lecturer of IEEE Circuit and Systems Society (97–99), the National Science Foundation CAREER Award in 1996, and the 1994 Darlington Best Paper Award from the IEEE Circuits and Systems society. From 1997–99 and 2000–2002, he served as an Associate Editor for IEEE Transaction on Circuits and Systems: Part II and an Associate Editor for the IEEE Transactions on VLSI, respectively. He was the technical program chair for the 2002 IEEE Workshop on Signal Processing Systems (SiPS02).     

TD-LTE:抢占无线全新商机带动全球发展势态

LTE是目前大部分电信运营商首选的下一代移动通信技术,已有100多家运营商承诺将于2010年开始部署LTE.不过,在非成对频段部署LTE的商机却常被忽略.