A Fast Recursive Algorithm and Architecture for Pruned Bit-reversal Interleavers

In this paper, pruned bit-reversal permutations employed in variable-length interleavers and their associated fast pruning algorithms and architectures are considered. Pruning permutations is mathematically formulated as a counting problem in a set of k integers and any subset of $\alpha $ consecutive integers under some permutation, where integers from this subset that map into indices less than some $\beta <k$ are to be counted. A solution to this problem using sums involving integer floors and related functions is proposed. It is shown that these sums can be evaluated recursively using integer operations. Specifically, a mathematical treatment for bit-reversal permutations (BRPs) and their permutation statistics are presented. These permutations have been mainly addressed using numerical techniques in the literature to speed up in-place computations of fast Fourier and related transforms. Closed-form expressions for BRP statistics including inversions, serial correlations, and a new statistic called permutation inliers that characterizes the pruning gap of pruned interleavers, are derived. Using the inliers statistic, a recursive algorithm that computes the minimum number of inliers in a pruned BR interleaver (PBRI) in logarithmic time complexity is presented. This algorithm enables parallelizing a serial PBRI algorithm by any desired parallelism factor by computing the pruning gap in lookahead rather than a serial fashion, resulting in significant reduction in interleaving latency and memory overhead. Extensions to 2-D block and stream interleavers are also presented. Moreover, efficient hardware architectures for the proposed algorithms employing simple logic gates are presented. Simulation results of interleavers employed in modern communication standards demonstrate 3 to 4 orders of magnitude improvement in interleaving time compared to existing approaches.     

Parallel lookahead algorithms for pruned interleavers

In this letter, the design of efficient parallel pruned channel and turbo interleavers for Ultra Mobile Broadband (UMB) physical layer standard [1] is addressed. Channel interleaving is based on a bit-reversal algorithm in which addresses are mapped from linear order into bit-reversed order. Turbo interleaving is based on filling a 2D array row by row, interleaving each row independently using a linear congruential sequence (LCS), bit-reversing the order of the rows, and then reading the interleaved addresses column by column. To accommodate for flexible codeword lengths L, interleaving is done using a mother interleaver of length M = 2ⁿ, where n is the smallest integer such that L ⩽ M, such that outlier interleaved addresses greater than L - 1 get pruned away. This pruning operation creates a serial bottleneck since the interleaved address of a linear address χ is now a function of the interleaving operation as well as the number of pruned addresses up to χ. A generic parallel lookahead pruned interleaving scheme that breaks this dependency is proposed. The efficiency of the proposed scheme is demonstrated in the context of both UMB interleavers. An iterative pruned bit-reversal algorithm that interleaves any address in O(log L) steps is presented. Moreover, an iterative pruned turbo interleaving algorithm based on LCSs that interleaves any address in O(log² L) steps is presented.     

Formation of silicon nanocrystals by thermal annealing of low-pressure chemical-vapor deposited amorphous SiNx (x=0.16) thin films

Silicon nanocrystals have been produced by thermal annealing of SiN_x thin film obtained by low pressure chemical vapor deposition using a mixture between disilane and ammonia. Morphological, structural, and photoluminescence properties of the thin film were investigated using X-ray diffraction, scanning electron microscopy, Raman spectroscopy and photoluminescence spectroscopy. The results revealed a high crystallinity of film with a crystalline volume fraction exceeded 70%, and a dominance of silicon nanocrystallites having the sizes within the range 2.5–5 nm and density ~1.98.10¹²/cm². The PL peaks consist of nanocrystalline silicon and amorphous silicon. The luminescence from the silicon nanocrystals was dominant.     

Design and testing of SMA temperature-compensated cavity resonators

In this paper, we present a method for designing temperature-compensated cavity resonators using shape memory alloys (SMAs). This paper gives an expression for the temperature drift of resonant frequency, which is valid for any conductor-loaded cavity regardless of its shape. This formula, combined with a field perturbation model, is used to derive the resonant frequency of an SMA-compensated resonator subject to temperature fluctuation. Experimental results are given that confirm the feasibility of the proposed design approach. A design method is proposed for specifying SMA alloys to build the actuator. An expression is derived to accurately predict the performance of an actuator design.     

Superconducting millimeter-wave E-plane filters

The authors report on the measured performance of a three-pole E-plane filter constructed from high-T_c superconducting bulk materials at 34.5 GHz. Experimental results are presented for the insertion loss and return loss of the filter at 77 K. The problems associated with the use of bulk materials at the millimeter-wave range are addressed. Other possible superconducting waveguide filter configurations are proposed. While the experimental results are taken at low input power level, the current distribution inside the filter structure is calculated, and the power handling capability of the superconducting filter is discussed     

Non-Intrusive Online Quality of Experience Assessment for Voice Communications

Recently user quality of experience (QoE) is employed in evaluating end user satisfaction in communications systems. Generally, current approaches for QoE assessment are obtrusive, laboratory based and offline. Estimation of user satisfaction in static manner based on mean opinion score is not directly related to instantaneous individual end user contentment. In this paper, based on correlations between user’s physiological signals and her/his feelings about the service quality, a non-intrusive and user centric QoE assessment system for voice communications is developed. The findings of this study indicate that the emotional patterns in response to the changes in channel quality can be adapted to estimate the level of satisfaction in a QoE assessment system in a live manner. Based on experimental results, two categories of users are identified: sensitive and insensitive towards quality degradations. The results indicate that for the sensitive users, our non-intrusive subjective quality assessment method outperforms ITU-T P.563 standard with respect to root mean square error; while, the results are much better among the insensitive users.     

A Novel Design Methodology for High-Performance Programmable Decoder Cores for AA-LDPC Codes

A new parameterized-core-based design methodology targeted for programmable decoders for low-density parity-check (LDPC) codes is proposed. The methodology solves the two major drawbacks of excessive memory overhead and complex on-chip interconnect typical of existing decoder implementations which limit the scalability, degrade the error-correction capability, and restrict the domain of application of LDPC codes. Diverse memory and interconnect optimizations are performed at the code-design, decoding algorithm, decoder architecture, and physical layout levels, with the following features: (1) Architecture-aware (AA)-LDPC code design with embedded structural features that significantly reduce interconnect complexity, (2) faster and memory-efficient turbo-decoding algorithm for LDPC codes, (3) programmable architecture having distributed memory, parallel message processing units, and dynamic/scalable transport networks for routing messages, and (4) a parameterized macro-cell layout library implementing the main components of the architecture with scaling parameters that enable low-level transistor sizing and power-rail scaling for power-delay-area optimization. A 14.3 mm² programmable decoder core for a rate-1/2, length 2048 AA-LDPC code generated using the proposed methodology is presented, which delivers a throughput of 6.4 Gbps at 125 MHz and consumes 787 mW of power.Mohammad M. Mansour received his B.E. degree with distinction in 1996 and his M.S. degree in 1998 all in Computer and Communications Engineering from the American University of Beirut (AUB). In August 2002, he received his M.S. degree in Mathematics from the University of Illinois at Urbana-Champaign (UIUC). Mohammad received his Ph.D. in Electrical Engineering in May 2003 from UIUC. He is currently an Assistant Professor of Electrical Engineering with the ECE department at AUB. From 1998 to 2003, he was a research assistant at the Coordinated Science Laboratory (CSL) at UIUC. In 1997 he was a research assistant at the ECE department at AUB, and in 1996 he was a teaching assistant at the same department. From 1992–1996 he was on the Deans honor list at AUB. He received the Harriri Foundation award twice in 1996 and 1998, the Charli S. Korban award twice in 1996 and 1998, the Makhzoumi Foundation Award in 1998, and the PHI Kappa PHI Honor Society awards in 2000 and 2001. During the summer of 2000, he worked at National Semiconductor Corp., San Francisco, CA, with the wireless research group. His research interests are VLSI architectures and integrated circuit (IC) design for communications and coding theory applications, digital signal processing systems and general purpose computing systems.Naresh R. Shanbhag received the B.Tech from the Indian Institute of Technology, New Delhi, India, in 1988, M.S. from Wright State University and Ph.D. degree from the University of Minnesota, in 1993, all in Electrical Engineering. From July 1993 to August 1995, he worked at AT&T Bell Laboratories at Murray Hill in the Wide-Area Networks Group, where he was responsible of development of VLSI algorithms, architectures and implementation for high-speed data communications applications. In particular, he was the lead chip architect for AT&Ts 51.84 Mb/s transceiver chips over twisted-pair wiring for Asynchronous Transfer Mode (ATM)-LAN and broadband access. Since August 1995, he is with the Department of Electrical and Computer Engineering, and the Coordinated Science Laboratory where he is presently an Associate Professor and Director of the Illinois Center for Integrated Microsystems. At University of Illinois, he founded the VLSI Information Processing Systems (ViPS) Group, whose charter is to explore issues related to low-power, high-performance, and reliable integrated circuit implementations of broadband communications and digital signal processing systems. He has published numerous journal articles/book chapters/conference publications in this area and holds three US patents. He is also a co-author of the research monograph Pipelined Adaptive Digital Filters (Norwell, MA: Kluwer, 1994). Dr. Shanbhag received the 2001 IEEE Transactions Best Paper Award, 1999 Xerox Faculty Research Award, 1999 IEEE Leon K. Kirchmayer Best Paper Award, the 1997 Distinguished Lecturer of IEEE Circuit and Systems Society (97–99), the National Science Foundation CAREER Award in 1996, and the 1994 Darlington Best Paper Award from the IEEE Circuits and Systems society. From 1997–99 and 2000–2002, he served as an Associate Editor for IEEE Transaction on Circuits and Systems: Part II and an Associate Editor for the IEEE Transactions on VLSI, respectively. He was the technical program chair for the 2002 IEEE Workshop on Signal Processing Systems (SiPS02).     

Frequency- and time-varying scattering parameters of a photo-excited superconducting microbridge

The extended scattering parameters for linear time varying devices are used to model a high-temperature superconducting (HTS) bridge under time-harmonic optical irradiation. It is shown that this structure acts as a time-varying low-pass filter, which its transfer function characteristic changes periodically with time. This behavior makes this configuration ideal for applications where a time-varying filter is on demand.     

A Reconfigurable TDMP Decoder for Raptor Codes

A Raptor code is a concatenation of a fixed rate precode and a Luby-Transform (LT) code that can be used as a rateless error-correcting code over communication channels. By definition, Raptor codes are characterized by irregularity features such as dynamic rate, check-degree variability, and joint coding, which make the design of hardware-efficient decoders a challenging task. In this paper, serial turbo decoding of architecture-aware Raptor codes is mapped into sequential row processing of a regular matrix by using a combination of code enhancements and architectural optimizations. The proposed mapping approach is based on three basic steps: (1) applying systematic permutations on the source matrix of the Raptor code, (2) confining LT random encoding to pseudo-random permutation of messages and periodic selection of row-splitting scenarios, and (3) developing a reconfigurable parallel check-node processor that attains a constant throughput while processing LT- and LDPC-nodes of varying degrees and count. The decoder scheduling is, thus, made simple and uniform across both LDPC and LT decoding. A serial decoder implementing the proposed approach was synthesized in 65 nm, 1.2 V CMOS technology. Hardware simulations show that the decoder, decoding a rate-0.4 code instance, achieves a throughput of 36 Mb/s at SNR of 1.5 dB, dissipates an average power of 27 mW and occupies an area of 0.55 mm².