Fabrication of polymeric large-core waveguides for opticalinterconnects using a rubber molding process

Polymeric large-core (47 μm×41 μm) optical waveguides for optical interconnects have been fabricated by using a rubber molding process. For low-cost low-loss large-core waveguides, our newly developed thick-photoresist patterning process is used for a master fabrication. Also a low-loss thermocurable polymer, perfluorocyclobutane (PFCB), is used in fabricating optical waveguides by rubber molding for the first time. The propagation loss is measured to be 0.4 dB/cm at the wavelength of 1.3 μm, and 0.7 dB/cm at the wavelength of 1.55 μm     

A new on-chip interconnect crosstalk model and experimentalverification for CMOS VLSI circuit design

A new, simple closed-form crosstalk model is proposed. The model is based on a lumped configuration but effectively includes the distributed properties of interconnect capacitance and resistance. CMOS device nonlinearity is simply approximated as a linear device. That is, the CMOS gate is modeled as a resistance at the driving port and a capacitance at a driven port. Interconnects are modeled as effective resistances and capacitances to match the distributed transmission behavior. The new model shows excellent agreement with SPICE simulations. Further, while existing models do not support the multiple line crosstalk behaviors, our model can be generalized to multiple lines. That is, unlike previously published work, even if the geometrical structures are not identical, it can accurately predict crosstalk. The model is experimentally verified with 0.35-μm CMOS process-based interconnect test structures. The new model can be readily implemented in CAD analysis tools. This model can be used to predict the signal integrity for high-speed and high-density VLSI circuit design     

Watt-level Ka- and Q-band MMIC power amplifiers operating at lowvoltages

Ka- and Q-band watt-level monolithic power amplifiers (PAs) operating at a low drain bias of 3.6 V are presented in this paper. Design considerations for low-voltage operation have been carefully studied, with an emphasis on the effect of device models. The deficiency of conventional table-based models for low-voltage operation is identified. A new nonlinear device model, which combines the advantages of conventional analytical models and table-based models, has been developed to circumvent the numerical problems and, thus, to predict optimum load impedance accurately. The model was verified with load-pull measurements at 39 GHz. To implement a low-voltage 1-W monolithic-microwave integrated-circuit amplifier, careful circuit design has been performed using this model. A Q-band two-stage amplifier showed 1-W output power with a high power gain of 15 dB at 3.6-V drain bias. The peak power-added efficiency (PAE) was 28.5% and 1-dB compression power (P_{1 dB}) was 29.7 dBm. A Ka-band two-stage amplifier showed a P_{1 dB} of 30 dBm with 24.5-dB associated gain and 32.5% PAE. Under very low dc power conditions (P_dc<2 W, V_ds=3.4 V), the amplifiers showed 29-dBm output power and PAE close to 36%, demonstrating ultimate low-power operation capability. To the best of our knowledge, this is the first demonstration of watt-level PA's under 3.6-V operation at 26 and 40 GHz. Compared with the published data, this work also represents state-of-the-art performance in terms of power gain, efficiency, and chip size     

Characterizing Overlay Multicast Networks and Their Costs

Overlay networks among cooperating hosts have recently emerged as a viable solution to several challenging problems, including multicasting, routing, content distribution, and peer-to-peer services. Application-level overlays, however, incur a performance penalty over router-level solutions. This paper quantifies and explains this performance penalty for overlay multicast trees via: 1) Internet experimental data; 2) simulations; and 3) theoretical models. We compare a number of overlay multicast protocols with respect to overlay tree structure, and underlying network characteristics. Experimental data and simulations illustrate that the mean number of hops and mean per-hop delay between parent and child hosts in overlay trees generally decrease as the level of the host in the overlay tree increases. Overlay multicast routing strategies, overlay host distribution, and Internet topology characteristics are identified as three primary causes of the observed phenomenon. We show that this phenomenon yields overlay tree cost savings: Our results reveal that the normalized cost L(n)/U(n) is propn^0.9 for small n, where L(n) is the total number of hops in all overlay links, U(n) is the average number of hops on the source to receiver unicast paths, and n is the number of members in the overlay multicast session. This can be compared to an IP multicast cost proportional to n^0.6 to n^0.8     

A Multi‐Functional Highly Efficient Upconversion Luminescent Film with an Array of Dielectric Microbeads Decorated with Metal Nanoparticles

Upconversion nanoparticles (UCNPs) have been integrated with photonic platforms to overcome the intrinsically low quantum efficiency limit of upconversion luminescence (UCL). However, platforms based on thin films lack transferability and flexibility, which hinders their broader and more practical application. A plasmonic structure is developed that works as a multi‐functional platform for flexible, transparent, and washable near‐infrared (NIR)‐to‐visible UCL films with ultra‐strong UCL intensity. The platform consists of dielectric microbeads decorated with plasmonic metal nanoparticles on an insulator/metal substrate. Distinct improvements in NIR confinement, visible light extraction, and boosted plasmonic effects for upconversion are observed. With weak NIR excitation, the UCL intensity is higher by three orders of magnitude relative to the reference platform. When the microbeads are organized in a square lattice array, the functionality of the platform can be expanded to wearable and washable UCL films. The platform can be transferred to transparent, flexible, and foldable films and still emit strong UCL with a wide viewing angle.     

Microlens for efficient coupling between LED and optical fiber

A new fabrication method of a microlens is proposed that can be easily applied to optical devices and microlens systems. The proposed microlens is formed by self-surface tension and cohesion of UV curing material. Since the microlens is hardened by short time UV exposure, the fabrication process is very simple. Integration with surface emitting-light emitting diode (SE-LED) results in enhanced coupling to optical fiber with coupling efficiency larger than the conventional case by 1.5 times. We also made a hemispheric microlensed fiber using this method. Compared with a typical arc-lensed fiber and a flat-end fiber, the coupling efficiency is improved to 18% and 40%, respectively     

A power-factor controller for single-phase PWM rectifiers

A novel power-factor controller for single-phase pulsewidth modulated rectifiers is proposed. The unity power-factor controller for a sinusoidal input current is derived using the feedback linearization concept. Two active switches and two diodes are utilized for AC-to-DC power conversion. Experimental results obtained on a 4 kW prototype are discussed     

A 16-Bit by 16-Bit MAC Design Using Fast 5:3 Compressor Cells

3:2 counters and 4:2 compressors have been widely used for multiplier implementations. In this paper, a fast 5:3 compressor is derived for high-speed multiplier implementations. The fast 5:3 compression is obtained by applying two rows of fast 2-bit adder cells to five rows in a partial product matrix. As a design example, a 16-bit by 16-bit MAC (Multiply and Accumulate) design is investigated both in a purely logical gate implementation and in a highly customized design. For the partial product reduction, the use of the new 5:3 compression leads to 14.3% speed improvement in terms of XOR gate delay. In a dynamic CMOS circuit implementation using 0.225 m bulk CMOS technology, 11.7% speed improvement is observed with 8.1% less power consumption for the reduction tree.