A 231-MHz, 2.18-mW 32-bit Logarithmic Arithmetic Unit for Fixed-Point 3-D Graphics System

A 32-bit fixed-point logarithmic arithmetic unit is proposed for the possible application to mobile three-dimensional (3-D) graphics system. The proposed logarithmic arithmetic unit performs division, reciprocal, square-root, reciprocal-square-root and square operations in two clock cycles and powering operation in four clock cycles. It can program its number range for accurate computation flexibility of 3-D graphics pipeline and eight -region piecewise linear approximation model for logarithmic and antilogarithmic conversion to reduce the operation error under 0.2%. Its test chip is implemented by 1-poly 6-metal 0.18-mum CMOS technology with 9-k gates. It operates at the maximum frequency of 231 MHz and consumes 2.18 mW at 1.8-V supply     

Why does it pay to be selfish in a MANET?

Routing protocols for a mobile ad hoc network have assumed that all mobile nodes voluntarily participate in forwarding others' packets. This was a reasonable assumption because all MNs in a MANET belonged to a single authority. In the near future, however, a MANET may consist of MNs that belong to many different organizations since numerous civilian applications are expected to crop up. In this situation, some MNs may run independently and purposely decide not to forward packets so as to save their own energy. This could potentially lead to network partitioning and corresponding performance degradation. To minimize such situations in MANETs, many studies have explored the use of both the carrot and the stick approaches by having reputation-based, credit-payment, and game theory schemes. This article summarizes existing schemes, identifies their relative advantages, and projects future directions     

Compact 2.5 Gb/s Burst‐Mode Receiver with Optimum APD Gain for XG‐PON1 and GPON Applications

This letter presents a compact 2.5 Gb/s burst‐mode receiver using the first reported monolithic amplifier IC developed with 0.25 …m SiGe BiCMOS technology. With optimum avalanche photodiode gain, the receiver module can obtain a fast response, high sensitivity and wide dynamic range, satisfying the overhead timing and various power specifications for a 2.5 Gb/s next‐generation passive optical network (PON), as well as a legacy 1.25 Gb/s PON in the upstream.     

Low‐Power Nonvolatile Charge Storage Memory Based on MoS2 and an Ultrathin Polymer Tunneling Dielectric

Low‐power, nonvolatile memory is an essential electronic component to store and process the unprecedented data flood arising from the oncoming Internet of Things era. Molybdenum disulfide (MoS₂) is a 2D material that is increasingly regarded as a promising semiconductor material in electronic device applications because of its unique physical characteristics. However, dielectric formation of an ultrathin low‐k tunneling on the dangling bond‐free surface of MoS₂ is a challenging task. Here, MoS₂‐based low‐power nonvolatile charge storage memory devices are reported with a poly(1,3,5‐trimethyl‐1,3,5‐trivinyl cyclotrisiloxane) (pV3D3) tunneling dielectric layer formed via a solvent‐free initiated chemical vapor deposition (iCVD) process. The surface‐growing polymerization and low‐temperature nature of the iCVD process enable the conformal growing of low‐k (≈2.2) pV3D3 insulating films on MoS₂. The fabricated memory devices exhibit a tunable memory window with high on/off ratio (≈10⁶), excellent retention times of 10⁵ s with an extrapolated time of possibly years, and an excellent cycling endurance of more than 10³ cycles, which are much higher than those reported previously for MoS₂‐based memory devices. By leveraging the inherent flexibility of both MoS₂ and polymer dielectric films, this research presents an important milestone in the development of low‐power flexible nonvolatile memory devices.     

Alias-Free Subband Adaptive Filtering With Critical Sampling

To overcome the limitations of a conventional fullband adaptive filtering, various subband adaptive filtering (SAF) structures have been proposed. Properly designed, an SAF will converge faster at a lower computational cost than a fullband structure. However, its design should consider the following two facts: the interband aliasing introduced by the downsampling process degrades its performance, and the filter bank in the SAF introduces additional computational overhead and system delay. In this paper, to fully exploit the benefits of using an SAF, an almost alias-free SAF structure with critical sampling is proposed. The interband alising is removed from the subband signal by isolating the aliasing using a bandwidth-increased analysis filter. Computer simulations show that the proposed structure converges faster than both an equivalent fullband structure at lower computational complexity and recently proposed SAF structures for a colored input.     

Room-Temperature-Processable Highly Reliable Resistive Switching Memory with Reconfigurability for Neuromorphic Computing and Ultrasonic Tissue Classification

Reversible metal-filamentary mechanism has been widely investigated to design an analog resistive switching memory (RSM) for neuromorphic hardware-implementation. However, uncontrollable filament-formation, inducing its reliability issues, has been a fundamental challenge. Here, an analog RSM with 3D ion transport channels that can provide unprecedentedly high reliability and robustness is demonstrated. This architecture is realized by a laser-assisted photo-thermochemical process, compatible with the back-end-of-line process and even applicable to a flexible format. These superior characteristics also lead to the proposal of a practical adaptive learning rule for hardware neural networks that can significantly simplify the voltage pulse application methodology even with high computing accuracy. A neural network, which can perform the biological tissue classification task using the ultrasound signals, is designed, and the simulation results confirm that this practical adaptive learning rule is efficient enough to classify these weak and complicated signals with high accuracy (97%). Furthermore, the proposed RSM can work as a diffusive-memristor at the opposite voltage polarity, exhibiting extremely stable threshold switching characteristics. In this mode, several crucial operations in biological nervous systems, such as Ca²⁺ dynamics and nonlinear integrate-and-fire functions of neurons, are successfully emulated. This reconfigurability is also exceedingly beneficial for decreasing the complexity of systems—requiring both drift- and diffusive-memristors.     

Variable VCC design techniques forbattery-operated DRAMs

Wide-voltage-range DRAMs with extended data retention are desirable for battery-operated or portable computers and consumer devices. The techniques required to obtain wide operation, functionality, and performance of standard DRAMs from 1.8 V (two NiCd or alkaline batteries) to 3.6 V (upper end of LVTTL standard) are described. Specific techniques shown are: (1) a low-power and low-voltage reference generator for detecting V_CC level; (2) compensation of DC generators, V_BB and V_PP, for obtaining high speed at reduced voltages; (3) a static word-line driver and latch-isolation sense amplifier for reducing operating current; and (4) a programmable V_CC variable self-refresh scheme for obtaining maximum data retention time over a full operating range. A sub-50-ns access time is obtained for a 16 M DRAM (2 M×8) by simulation     

Monolithic arrays of surface emitting laser NOR logic devices

Monolithic, cascadable, laser-logic-device arrays have been realized and characterized. The monolithic surface-emitting laser logic (SELL) device consists of an AlGaAs superlattice lasing around 780 nm connected to a heterojunction phototransistor (HPT) in parallel and a resistor in series. Arrays up to 8×8 have been fabricated, and 2×2 arrays show uniform characteristics. The optical logic output is switched off with 40 μW incident optical input     

A fast parallel squarer based on divide-and-conquer

Fast and small squarers are needed in many applications such as image compression. A new family of high-performance parallel squarers based on the divide-and-conquer method is reported. Our main result was realized for the basis cases of the divide-and-conquer recursion by using optimized n-bit primitive squarers, where n is in the range of two to six. This method reduced the gate count and provided shorter critical paths. A chip implementing an 8-b squarer was designed, fabricated, and successfully tested, resulting in 24 million operations per second (MOPS) using a 2-μm CMOS fabrication technology. This squarer had two additional features: increased number of squaring operations per unit circuit area and the potential for reduced power consumption per squaring operation     

A Novel and Efficient Feature Extraction Method for Iris Recognition

With a growing emphasis on human identification, iris recognition has recently received increasing attention. Iris recognition includes eye imaging, iris segmentation, verification, and so on. In this letter, we propose a novel and efficient iris recognition method which employs a cumulative‐sum‐based grey change analysis. Experimental results demonstrate that the proposed method can be used for human identification in efficient manner.