Electrical properties of HgCdTe epilayers doped with silver using an AgNO3 solution

We employed AgNO₃ solutions for doping Ag in liquid phase epitaxy (LPE) grown Hg_0.78Cd_0.22Te epilayers and found that the minority carrier lifetimes became longer so that the diode properties improved. After annealing LPE grown Hg(1-x)Cd(x)Te layers (x=0.22) in Hg atmosphere, the epilayers were immersed in an AgNO₃ solution at room temperature. The typical carrier concentrations of holes was 3 × 10¹⁶ cm⁻³ at 77K. These values were almost the same as for the nondoped wafers. Also, its acceptor level was 3 to 4 meV. This shows that the Ag was activated. The doped crystals have lifetimes several times longer than those of the nondoped crystals. Numerical fitting showed the lifetime was limited mostly by the Auger 7 process. The Shockley-Read-Hall recombination process was not effective. To examine the Ag-doped wafer, we fabricated photodiodes using standard planar technology. The diodes have an average zero-bias resistance of several MΩ and a shunt resistance of about 1 GΩ for a 10 μm cutoff wavelength at 78K. These values are about four times higher than those of nondoped diodes. The photo current is also two times higher at the same pixel size. This shows that the quantum efficiency is increased. The extension of the lifetime contributes to the high resistance and the high quantum efficiency of the photodiode.     

Formation of uniform GaAs multi-atomic steps with 20–30 nm periodicity and related structures on vicinal (111)B planes by MBE

We studied morphology of GaAs surfaces and the transport properties of two-dimensional electron gas (2DEG) on vicinal (111)B planes. Multi-atomic steps (MASs) are found on the vicinal (111)B facet grown by molecular beam epitaxy, which will affect electron transport on the facet. We also studied how the morphology of GaAs epilayers on vicinal (111)B substrates depends on growth conditions, especially on the As₄ flux. The uniformity of MASs on the substrates have been improved and smooth surfaces were obtained when the GaAs was grown with high As₄ flux, providing step periodicity of 20 nm. The channel resistance of the 2DEG perpendicular to the MASs is reduced drastically with this smooth morphology. These findings are valuable not only for fabricating quantum devices on the (111)B facets but also those on the vicinal (111)B substrates.     

Analysis and discussion on conduction current based on simultaneousmeasurement of TSC and space charge distribution

A new analysis of conduction current distributed in dielectrics based on simultaneous measurements of thermally stimulated current (TSC) and time dependent space charge distribution is proposed. A new system pulsed electro-acoustic (PEA) method has been developed to enable simultaneous measurement of the TSC and the dynamic space charge and electric field distributions as a function of temperature within insulators. With the new system, the relationship between the TSC and the time dependent electric field distribution in electron beam (e-beam) irradiated PMMA has been investigated. From the time dependent electric field, the displacement current in dielectrics is obtained. The TSC is a typical external current which is represented as an addition of the displacement current and a conduction current in dielectrics. This paper makes it clear that the conduction current as a function of position is determined by the simultaneous measurement of the external current and the dynamic space charge distribution     

Blue electroluminescent devices withSrGa2S4:Ce for full-color display

In order to realize full-color electroluminescent (EL) displays, which are expected as a dominant candidate for the future multimedia flat panel display, blue EL devices with SrGa₂S₄:Ce have been prepared by molecular beam epitaxy (MBE). This paper proposes a novel deposition method employing Sr metal and Ga₂S₄ compound as the source materials. A single-phase SrGa₂S₄ layer is obtained in a Ga₂S₃/Sr flux ratio of 60 and at the growth temperature of 560°C. We have obtained the well-saturated blue with CIE color coordinates of x=0.14, y=0.14 and brighter blue EL devices made by optimizing the growth conditions in MBE. The maximum luminance of 70 cd/m² in comparison with the 3 cd/m₂ of our previous EL devices, is achieved at a driving frequency of 1 kHz     

Simulation of a high performance MOSFET with a quantum wirestructure incorporating a periodically bent Si-SiO2 interface

A MOSFET using a serrated quantum wire structure that produces one-dimensional electron confinement shows excellent subthreshold characteristics and enhanced drive capability compared to a conventional MOSFET with a flat Si-SiO₂ interface. We studied the quantum wire structure with its periodically bent Si-SiO₂ interface using simulations. The potential in the convex regions of the silicon is 0.34 V higher than that in the concave ones when the bending angle is 90°, the bending period is 100 nm, substrate doping is 3.0×10 ¹⁷ cm^-3, and a gate voltage is 0.1 V. Because of this increase in potential in the convex regions, electrons are confined in a narrow width of 13 nm in the convex regions. This 1-D electron confinement effect by the bent Si-SiO₂ interface is clearly observed at low gate voltage and is reduced as the gate voltage becomes higher. Due to the confinement effect, drain current in the MOSFET with this quantum wire structure is 270 times higher than that of a MOSFET with a flat Si-SiO₂ interface at a gate voltage of 0.05 V. In addition, the short-channel effect is more effectively suppressed in this MOSFET than in a conventional MOSFET     

Still image transmission using ARQ over Rayleigh fading channels

The authors propose a new ARQ scheme suitable for image transmission over radio channels. The proposed scheme detects only serious degradation and so attains higher throughput performance than the conventional ARQ scheme     

Failure-analysis-based test chip design for quick yield improvement

A new design approach for a test chip developed to shorten the debugging cycle time in fabrication is described. This approach meets the requirements for failure analysis as well as parametric and statistical analyses. Particular attention is devoted to accurate defect density estimation and to locating individual defects. This is done by designing test structures suitable for both electrical measurements and failure analysis. A specially designed test chip, named YTEG, is used to evaluate 0.5-μm CMOS process technologies, and confirms the effectiveness of the chip.     

Electrical properties of nickel in silicon

Electrical activity and energy levels as well as diffusion properties of nickel in silicon have not yet been reliably established. In this paper, we investigated the diffusion and the electrical properties of nickel in silicon to confirm that nickel is electrically active and introduces one acceptor and one donor level by combined measurements of Hall coefficient and DLTS, and measurements of the distribution of electrically active nickel in various silicon diodes by DLTS. The former experiments show that bothn- andp- type silicon are compensated by nickel and that nickel introduces an acceptor level ofE _c-0.47 ± 0.04 eV and a donor level ofE _v +0.18 ± 0.02 eV. The concentrations of these two levels are almost identical over the diffusion temperatures from about 800 to 1100° C, indicating that these donor and acceptor levels are due to different charge states of the same nickel center. In the distribution measurements of electrically active nickel in silicon diodes, we inspected how nickel can be observed by DLTS. It was found that the nickel diffusion intop- n junction is rather complicated, the distribution profiles of nickel in the vicinity of thep- n junction being markedly influenced by an additional heating at elevated temperatures after the nickel diffusion. This gives evidence that the difference in silicon devices used in various studies could give rise to different results.     

An experimental 1.5-V 64-Mb DRAM

Low-voltage circuit technologies for higher-density dynamic RAMs (DRAMs) and their application to an experimental 64-Mb DRAM with a 1.5-V internal operating voltage are presented. A complementary current sensing scheme is proposed to reduce data transmission delay. A speed improvement of 20 ns was achieved when utilizing a 1.5-V power supply. An accurate and speed-enhanced half-V_CC voltage generator with a current-mirror amplifier and tri-state buffer is proposed. With it, a response time reduction of about 1.5 decades was realized. A word-line driver with a charge-pump circuit was developed to achieve a high boost ratio. A ratio of about 1.8 was obtained from a power supply voltage as low as 1.0 V. A 1.28 μm² crown-shaped stacked-capacitor (CROWN) cell was also made to ensure a sufficient storage charge and to minimize data-line interference noise. An experimental 1.5 V 64 Mb DRAM was designed and fabricated with these technologies and 0.3 μm electron-beam lithography. A typical access time of 70 ns was obtained, and a further reduction of 50 ns is expected based on simulation results. Thus, a high-speed performance, comparable to that of 16-Mb DRAMs, can be achieved with a typical power dissipation of 44 mW, one tenth that of 16-Mb DRAMs. This indicates that a low-voltage battery operation is a promising target for future DRAMs     

A 1 Mb EEPROM with MONOS memory cell for semiconductor diskapplication

A 1 Mb 5 V-only EEPROM (electrically erasable programmable ROM) with metal-oxide-nitride-oxide-semiconductor (MONOS) memory cells specifically designed for a semiconductor disk application is described. The memory has high endurance to write/erase cycles and a relatively low programming voltage of ±9 V. These advantages result from the structure and the characteristics of the MONOS memory cell. A newly developed dual-gate-type MONOS memory cell has a small unit cell area of 18.4 μm² with 1.2 μm lithography, and the die size of the fabricated chip is 5.3 mm×6.3 mm. A new programming scheme called multiblock erase solved the problem of slow programming speed. A programming speed of up to 1.1 μs/B equivalent (140 ms/chip) was obtained