Discrete Rayleigh distribution

Using a general approach for discretization of continuous life distributions in the univariate & bivariate situations, we have proposed a discrete Rayleigh distribution. This distribution has been examined in detail with respect to two measures of failure rate. Characterization results have also been studied to establish a direct link between the discrete Rayleigh distribution, and its continuous counterpart. This discretization approach not only expands the scope of reliability modeling, but also provides a method for approximating probability integrals arising out of a continuous setting. As an example, the reliability value of a complex system has been approximated. This discrete approximation in a nonnormal setting can be of practical use & importance, as it can replace the much relied upon simulation method. While the replication required is minimal, the degree of accuracy remains reasonable for our suggested method when compared with the simulation method.     

Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current

Wavelet transform has the property of resolving signal in both time and frequency unlike Fourier transform. In this work, we show that time-domain information obtained from wavelet analysis of supply current can be used to test the frequency specification of analog filters efficiently. The pole/zero locations in the frequency response of analog filters shift due to change in component values with process variations. It is essential to test the filters for the shift in frequency response and fix it during production test. Wavelet analysis of supply current can be a promising alternative to test frequency specification of analog filters, since it needs only one AC stimulus and is virtually unaffected by transistor threshold variation. Simulation results on two test circuits demonstrate that we can estimate pole/zero shift with less than 3% error using only one measurement, which requires about 18 measurements in the conventional technique.Swarup Bhunia received the undergraduate degree from Jadavpur University, Calcutta, India, and the Masters degree from the Indian Institute of Technology (IIT), Kharagpur. He is currently working toward the Ph.D. degree in the Department of Electrical Engineering, Purdue University, West Lafayette, IN, USA. He has worked in the EDA industry on RTL synthesis and verification for about three years. His research interest includes design methodologies for high-performance low-power testable VLSI system, defect-based testing, noise analysis, and noise-aware design.Arijit Raychowdhury received the B.E. degree in 2001 in electronics and telecommunication engineering from Jadavpur University, India. He is currently pursuing the Ph.D. degree in electrical and computer engineering in Purdue University, West Lafayette, IN, USA. He has worked as an analog circuit designer in Texas Instruments India. His research interests include device/circuit design for scaled silicon and nonsilicon devices. He has received academic excellence awards in 1997, 2000, and 2001 and Messner Fellowship from Purdue University in 2002. Mr. Raychowdhury has been awarded the Best Student Paper Award in the IEEE Nanotechnology Conference, 2003.Kaushik Roy received the B.Tech. degree in electronics and electrical communications engineering from the Indian Institute of Technology, Kharagpur, India, and the Ph.D. degree from the Electrical and Computer Engineering Department, University of Illinois, Urbana, in 1990. He was with the Semiconductor Process and Design Center of Texas Instruments, Dallas, TX, where he worked on FPGA architecture development and low-power circuit design. He joined the electrical and computer engineering faculty, Purdue University, West Lafayette, IN, in 1993, where he is currently a Professor. His research interests include VLSI design/CAD with particular emphasis in low-power electronics for portable computing and wireless communications, VLSI testing and verification, and reconfigurable computing. He has published more than 250 papers in refereed journals and conferences, holds six patents, and is Co-Author of a book on Low Power CMOS VLSI Design (New York: Wiley). He was Guest Editor for a Special Issue on Low-Power VLSI in IEE Proceedings Computers and Digital Techniques (July 2002). Dr. Roy received the National Science Foundation Career Development Award in 1995, the IBM Faculty Partnership Award, AT&T/Lucent Foundation Award, Best Paper Awards at the 1997 International Test Conference and 2000 International Symposium on Quality of IC Design, 2003 IEEE Latin American Test Workshop, and 2003 IEEE Nano. He is on the Editorial Board of IEEE Design and Test, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, and IEEE TRANSACTIONS ON VLSI SYSTEMS. He was Guest Editor for a Special Issue on Low-Power VLSI in IEEE DESIGN AND TEST (1994), and for the IEEE TRANSACTIONS ON VLSI SYSTEMS (June 2000).     

Parallel interference cancellation for uplink multirate overlay CDMA channels

To provide new and/or higher rate wireless services with limited spectrum resources, frequency overlay has been naturally proposed to accommodate the new and legacy systems in a common band. We address the multiuser detection problem for overlaid code-division multiple-access (CDMA) scenarios. However, in contrast to the well-studied conventional single-rate CDMA, miscellaneous systems overlay almost always indicates the presence of multirate traffic that introduces an additional degree of freedom in receiver design-i.e., differences in the symbol rates. We concentrate on receiver design for multirate traffic, while assuming a lack of information exchange between the constituent (new and legacy) systems, as is commonplace in practice. We propose a receiver architecture based on linear parallel interference cancellation where the out-of-rate intersystem interference is estimated and subtracted by means of its characteristic subspace, thereby avoiding the need for the exact knowledge of signature waveforms of the interfering system. Simulation results validate our solution and show that the proposed receiver has better performance in various aspects than several other solutions for the same purpose.     

Low-power scan design using first-level supply gating

Reduction in test power is important to improve battery lifetime in portable electronic devices employing periodic self-test, to increase reliability of testing, and to reduce test cost. In scan-based testing, a significant fraction of total test power is dissipated in the combinational block. In this paper, we present a novel circuit technique to virtually eliminate test power dissipation in combinational logic by masking signal transitions at the logic inputs during scan shifting. We implement the masking effect by inserting an extra supply gating transistor in the supply to ground path for the first-level gates at the outputs of the scan flip-flops. The supply gating transistor is turned off in the scan-in mode, essentially gating the supply. Adding an extra transistor in only one logic level renders significant advantages with respect to area, delay, and power overhead compared to existing methods, which use gating logic at the output of scan flip-flops. Moreover, the proposed gating technique allows a reduction in leakage power by input vector control during scan shifting. Simulation results on ISCAS89 benchmarks show an average improvement of 62% in area overhead, 101% in power overhead (in normal mode), and 94% in delay overhead, compared to the lowest cost existing method.     

Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation

This paper presents a novel design methodology for ultralow-power design using subthreshold leakage as the operating current (suitable for medium frequency of operation: tens to hundreds of millihertz). Standard design techniques suitable for super-threshold design can be used in the subthreshold region. However, in this study, it has been shown that a complete co-design at all levels of hierarchy (device, circuit, and architecture) is necessary to reduce the overall power consumption while achieving acceptable performance (hundreds of millihertz) in the subthreshold regime of operation. Simulation results of co-design on a five-tap finite-impulse-response filter shows /spl sim/2.5/spl times/ improvement in throughput at iso-power compared to a conventional design.     

Significant Enhancement of Proton Transport in Bioinspired Peptide Fibrils by Single Acidic or Basic Amino Acid Mutation

Bioinspired materials are extremely suitable for the development of biocompatible and environmentally friendly functional materials. Peptide‐based assemblies are remarkably attractive for such tasks, since they provide a simple way to fuse together functional and structural protein motifs in artificial materials. Motivated by this idea, it is shown here that the introduction of a single acidic, or basic, amino acid into the side chain of a heptameric self‐assembling peptide increases proton conduction in the resulting fibers by two orders of magnitude. This self‐doping effect is much more pronounced than the effect induced by the peptide's acidic and basic termini groups. Furthermore, the self‐doping process is found to be significantly more effective for acidic side chains than for basic ones due to both much more effective self‐doping process, resulting in an order of magnitude larger concentration of charge carriers for the acidic assemblies, and higher mobility of the formed charge carriers – almost threefolds in this case. This work facilitates the realization of unique bioinspired self‐assembled proton conducting materials that may find uses in the emerging bioprotonic technology. The presented design flexibility and, in particular, the ability to introduce both proton and proton holes further extend the usefulness of these materials.     

Novel Direct Nanopatterning Approach to Fabricate Periodically Nanostructured Perovskite for Optoelectronic Applications

While indirectly patterned organic–inorganic hybrid perovskite nanostructures have been extensively studied for use in perovskite optoelectronic devices, it is still challenging to directly pattern perovskite thin films because perovskite is very sensitive to polar solvents and high‐temperature environments. Here, a simple and low‐cost approach is proposed to directly pattern perovskite solid‐state films into periodic nanostructures. The approach is basically perovskite recrystallization through phase transformation with the presence of a periodic mold on an as‐prepared solid‐state perovskite film. Interestingly, this study simultaneously achieves not only periodically patterned perovskite nanostructures but also better crystallized perovskites and improved optical properties, as compared to its thin film counterpart. The improved optical properties can be attributed to the light extraction and increased spontaneous emission rate of perovskite gratings. By fabricating light‐emitting diodes using the periodic perovskite nanostructure as the emission layers, approximately twofold higher radiance and lower threshold than the reference planar devices are achieved. This work opens up a new and simple way to fabricate highly crystalline and large‐area perovskite periodic nanostructures for low‐cost production of high‐performance optoelectronic devices.     

Convergence properties and stationary points of a perceptronlearning algorithm

An analysis of the stationary (convergence) points of an adaptive algorithm that adjusts the perceptron weights is presented. This algorithm is identical in form to the least-mean-square (LMS) algorithm, except that a hard limiter is incorporated at the output of the summer. The algorithm is described in detail, a simple two-input example is presented, and some of its convergence properties are illustrated. When the input of the perceptron is a Gaussian random vector, the stationary points of the algorithm are not unique and they depend on the algorithm step size and the momentum constant. The stationary points of the algorithm are presented, and the properties of the adaptive weight vector near convergence are discussed. Computer simulations that verify the analysis are given     

Iris segmentation using game theory

Robust segmentation of an iris image plays an important role in iris recognition. However, the nonlinear deformations, pupil dilations, head rotations, motion blurs, reflections, nonuniform intensities, low image contrast, camera angles and diffusions, and presence of eyelids and eyelashes often hamper the conventional iris/pupil localization methods, which utilize the region-based or the gradient-based boundary-finding information. The novelty of this research effort is that we describe a new iris segmentation scheme using game theory to elicit iris/pupil boundaries from a nonideal iris image. We apply a parallel game-theoretic decision making procedure by modifying Chakraborty and Duncan??s algorithm, which integrates (1) the region-based segmentation and gradient-based boundary-finding methods and (2) fuses the complementary strengths of each of these individual methods. This integrated scheme forms a unified approach, which is robust to noise and poor localization, and less affected by weak iris/sclera boundaries. The verification and identification performance of the proposed method are validated using the ICE 2005, the UBIRIS Version 1, WVU Nonideal, and the CASIA Version 3 data sets.     

Design and investigations on a compact,UWB, monopole antenna with reconfigurable band notches for 5.2/5.8 GHz WLAN and 5.5 GHz Wi‐MAX bands

This article represents a microstrip line–fed novel circular monopole antenna with ultra‐wideband (UWB) characteristics. The compact antenna provides reconfigurable notches at WLAN (5.2/5.8 GHz) and Wi‐MAX (5.5 GHz) frequency bands. The band rejection is achieved by etching an open‐ended L‐shaped slot in the ground plane, which effectively mitigates the interference between WLAN, Wi‐MAX, and UWB systems with an effective patch area of 36.26%. The proposed antenna operates from 3.05 to 12.11 GHz with VSWR 2 except at stopband (3.89‐5.93 GHz) to filter the WLAN and Wi‐MAX signals. The simulated return loss, gain, and radiation pattern of the proposed antenna has been experimentally verified with the fabricated one which holds a good agreement.