Passive alignment method of polymer PLC devices by using a hot embossing technique

A novel fabrication process using a hot embossing technique has been developed for micromechanical passive alignment of polymer planar lightwave circuit (PLC) devices. With only one step of embossing, single-mode waveguide straight channels and micropedestals for passive aligning are simultaneously defined on a polymer thin film with an accuracy of /spl plusmn/0.5 /spl mu/m. This process reduces the steps for fabricating alignment structures. A fabricated polymer PLC chip and fibers are combined on a v-grooved silicon optical bench (SiOB) in a flip-chip manner. The process provides a coupling loss as low as 0.67 dB per coupling face and a cost-effective packaging solution for various polymer PLC devices.     

High-performance MIM capacitor using ALD high-k HfO/sub 2/-Al/sub 2/O/sub 3/ laminate dielectrics

For the first time, we successfully fabricated and demonstrated high performance metal-insulator-metal (MIM) capacitors with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate dielectric using atomic layer deposition (ALD) technique. Our data indicates that the laminate MIM capacitor can provide high capacitance density of 12.8 fF//spl mu/m/sup 2/ from 10 kHz up to 20 GHz, very low leakage current of 3.2 /spl times/ 10/sup -8/ A/cm/sup 2/ at 3.3 V, small linear voltage coefficient of capacitance of 240 ppm/V together with quadratic one of 1830 ppm/V/sup 2/, temperature coefficient of capacitance of 182 ppm//spl deg/C, and high breakdown field of /spl sim/6 MV/cm as well as promising reliability. As a result, the HfO/sub 2/-Al/sub 2/O/sub 3/ laminate is a very promising candidate for next generation MIM capacitor for radio frequency and mixed signal integrated circuit applications.     

Transmission performance of 10-Gb/s 1550-nm transmitters using semiconductor optical amplifiers as booster amplifiers

We have demonstrated the transmission performance of 10-Gb/s transmitters based on LiNbO/sub 3/ modulator using semiconductor optical amplifiers (SOAs) as booster amplifiers. Utilizing the negative chirp converted in SOAs and self-phase modulation induced by high optical power, we can successfully transmit 10-Gb/s optical signals over 80 km through the standard single-mode fiber with the transmitter using SOAs as booster amplifiers. SOAs can be used for booster amplifiers with a careful adjustment of the operating conditions. In order to further understand an SOA's characteristics as a booster amplifier, we model SOAs and other subsystems to verify the experimental results. Based on the good agreement between the experimental and simulation results, we can find the appropriate parameters of input signals for SOAs, such as extinction ratio, rising/falling time, and chirp parameter to maximize output dynamic range and available maximum output power (P/sub o,max/).     

Geometric derivation of expectation-maximization and generalized successive interference cancellation algorithms with applications to CDMA channel estimation

The expectation-maximization (EM) algorithm is well established as a computationally efficient method for separable signal parameter estimation. Here, a new geometric derivation and interpretation of the EM algorithm is given that facilitates the understanding of EM convergence properties. Geometric considerations lead to an alternative separable signal parameter estimator based on successive cancellation. The new generalized successive interference cancellation (GSIC) algorithm is then applied to multiuser delay and channel estimation for code-division multiple access (CDMA) radiolocation and communication. The radiolocation application uses a handshaking protocol in which multiple reference nodes transmit acknowledge (ACK) CDMA packets to a master node, which then computes round-trip travel times (RTTs). Simulation results comparing EM and GSIC are presented for the CDMA channel-estimation problem.     

A study of the numerical dispersion relation for the 2-D ADI-FDTD method

This letter presents a numerical dispersion relation for the two-dimensional (2-D) finite-difference time-domain method based on the alternating-direction implicit time-marching scheme (2-D ADI-FDTD). The proposed analytical relation for 2-D ADI-FDTD is compared with those relations in the previous works. Through numerical tests, the dispersion equation of this work was shown as correct one for 2-D ADI-FDTD.     

Reliability investigation of 0.07-/spl mu/m InGaAs-InAlAs-InP HEMT MMICs with pseudomorphic In/sub 0.75/Ga/sub 0.25/As channel

The authors have investigated the reliability performance of G-band (183 GHz) monolithic microwave integrated circuit (MMIC) amplifiers fabricated using 0.07-/spl mu/m T-gate InGaAs-InAlAs-InP HEMTs with pseudomorphic In/sub 0.75/Ga/sub 0.25/As channel on 3-in wafers. Life test was performed at two temperatures (T/sub 1/ = 200 /spl deg/C and T/sub 2/ = 215 /spl deg/C), and the amplifiers were stressed at V/sub ds/ of 1 V and I/sub ds/ of 250 mA/mm in a N/sub 2/ ambient. The activation energy is as high as 1.7 eV, achieving a projected median-time-to-failure (MTTF) /spl ap/ 2 /spl times/ 10/sup 6/ h at a junction temperature of 125 /spl deg/C. MTTF was determined by 2-temperature constant current stress using /spl Delta/G/sub mp/ = -20% as the failure criteria. The difference of reliability performance between 0.07-/spl mu/m InGaAs-InAlAs-InP HEMT MMICs with pseudomorphic In/sub 0.75/Ga/sub 0.25/As channel and 0.1-/spl mu/m InGaAs-InAlAs-InP HEMT MMICs with In/sub 0.6/Ga/sub 0.4/As channel is also discussed. The achieved high-reliability result demonstrates a robust 0.07-/spl mu/m pseudomorphic InGaAs-InAlAs-InP HEMT MMICs production technology for G-band applications.     

Advanced disturbance observer design for mechanical positioning systems

Disturbance-observer (DOB)-based controller design is one of the most popular methods in the field of motion control. In this paper, the generalized disturbance compensation framework, named the robust internal-loop compensator (RIC) is introduced and an advanced design method of a DOB is proposed based on the RIC. The mixed sensitivity optimization problem, which is the main issue of DOB design, is also solved through the parametrization of the DOB in the RIC framework. Differently from conventional methods, the Q-filter is separated from the mixed sensitivity optimization problem and a systematic design law for the DOB is proposed. This guarantees the robustness and optimality of the DOB and enables the design for unstable plants.     

Wideband microstrip array antenna with sidelobe cancellationchannels

An antenna array for wideband operation (up to 70%) is presented. The structure has low windloading area and consists of parallel printed circuit boards (PCB) with microstrip dipoles, feed network and metal fences placed between the PCBs. The low profile, low weight antenna array forms the main beam and three difference patterns for sidelobe cancellation. Experimental results are compared with calculations for both microstrip dipole and array     

High-performance automatic target recognition through data-specificVLSI

Under the Mojave configurable computing project, we have developed a system for achieving high performance on an automatic target recognition (ATR) application through the use of configurable computing technology. The ATR system studied here involves real-time image acquisition from a synthetic aperture radar (SAR). SAR images exhibit statistical properties which can be used to improve system performance. In this paper, the Mojave configurable computing system uses field programmable gate arrays (FPGA's) to implement highly specialized circuits while retaining the flexibility of programmable components. A controller sequences through a set of specialized circuits in response to real-time events. Computer-aided design (CAD) tools have been developed to support the automatic generation of these specialized circuits. The resulting configurable computing system achieves a significant performance advantage over the existing solution, which is based on application specific integrated circuit (ASIC) technology