Bit-level systolic arrays for modular multiplication

This paper presents bit-level cellular arrays implementing Blakley's algorithm for multiplication of twon-bit integers modulo anothern-bit integer. The semi-systolic version uses 3n(n+3) single-bit carry save adders and 2n copies of 3-bit carry look-ahead logic, and computes a pair of binary numbers (C, S) in 3n clock cycles such thatC+S[0, 2N). The carry look-ahead logic is used to estimate the sign of the partial product, which is needed during the reduction process. The final result in the correct range [0,N) can easily be obtained by computingC+S andC+S–N, and selecting the latter if it is positive; otherwise, the former is selected. We construct a localized process dependence graph of this algorithm, and introduce a systolic array containing 3nw simple adder cells. The latency of the systolic array is 6n+w–2, wherew=n/2. The systolic version does not require broadcast and can be used to efficiently compute several modular multiplications in a pipelined fashion, producing a result in every clock cycle.     

On the performance of adaptive Gram-Schmidt algorithm forinterference cancelling arrays

A detailed performance analysis of the least mean square (LMS) algorithm to update each stage of an adaptive Gram-Schmidt processor in interference cancelling adaptive arrays is presented. It is shown that although the number of adaptive weights in the processor is proportional to M². the total misadjustment contributed by weight jittering is proportional to only M, where M is the size of the processor. In absolute terms, the weight jittering noises do not accumulate as would be expected, but cancel one another out and decrease in magnitude as the optimal powers become smaller from one processing stage to the next. For optimal performance, the feedback factors used in the individual LMS loops should be normalized so that the amount of misadjustment contributed and the convergence time constant are the same for all processing stages. All the weights belonging to one processing stage must be adjusted in a synchronous manner with the same input vector. This synchronous updating requirement is essential for the cancellation of the jittering noises, although in situations where the weights are adaptively updated in a time-multiplexed manner, it may appear more efficient to update each weight based on the most current inputs     

Millimetre wave performance of carbon-doped-base AlGaAs/GaAs HBTs

AlGaAs/GaAs HBTs with f/sub T/ of 52 GHz and f/sub max/ of 85 GHz have been obtained using a heavily-carbon-doped base layer. The HBT epitaxial layers were prepared by low-pressure MOVPE using carbon tetrachloride as the carbon source. To the author's knowledge, this work reports the first carbon-doped AlGaAs/GaAs HBTs with f/sub T/ and f/sub max/ greater than 50 GHz.<>     

Effects of CEE and Feedback Error on Performance for AF-ORS with PSA-CE Schemes Over Quasi-Static Rayleigh Fading Channels

In this paper, we propose the analytical approach for amplify-and-forward (AF) opportunistic relaying schemes (ORS). When operation of AF-ORS consists of relay selection and data transmission phases based on pilot symbol assisted-channel estimation (PSA-CE) methods over quasi-static Rayleigh fading channels, we show that the relay selection phase can be implemented by pilots symbols transmission for source-relay and relay-destination. Moreover, the feedback method for the selected relay index is proposed to have a simple fashion. Then, we investigate the effects of both a channel estimation error and an estimated noise variance, which are obtained by PSA-CE methods, on the received signal-to-noise ratio (SNR). The average SNR loss is also derived in terms with the number of pilots in PSA-CE methods. Moreover, the average symbol error rate, the outage probability, and the normalized channel capacity of the ORS are derived in approximated closed-form expressions for an arbitrary link SNR when the channel state information in the source-relay-destination link is estimated based on transmitted pilots symbols. As the number of pilot symbols, the derived analytical approach is verified, and by comparing it with simulation results, the accuracy is demonstrated. In addition, it is verified that the effect of the feedback error can be neglected for PAS-CE methods over quasi-static fading channels.     

Effects of Interfacial Dielectric Layers on the Electrical Performance of Top‐Gate In‐Ga‐Zn‐Oxide Thin‐Film Transistors

We investigate the effects of interfacial dielectric layers (IDLs) on the electrical properties of top‐gate In‐Ga‐Zn‐oxide (IGZO) thin film transistors (TFTs) fabricated at low temperatures below 200°C, using a target composition of In:Ga:Zn = 2:1:2 (atomic ratio). Using four types of TFT structures combined with such dielectric materials as Si₃N₄ and Al₂O₃, the electrical properties are analyzed. After post‐annealing at 200°C for 1 hour in an O₂ ambient, the sub‐threshold swing is improved in all TFT types, which indicates a reduction of the interfacial trap sites. During negative‐bias stress tests on TFTs with a Si3N4 IDL, the degradation sources are closely related to unstable bond states, such as Si‐based broken bonds and hydrogen‐based bonds. From constant‐current stress tests of Id = 3 µA, an IGZO‐TFT with heat‐treated Si₃N₄ IDL shows a good stability performance, which is attributed to the compensation effect of the original charge‐injection and electron‐trapping behavior.     

Decimal SRT Square Root: Algorithm and Architecture

Given the popularity of decimal arithmetic, hardware implementation of decimal operations has been a hot topic of research in recent decades. Besides the four basic operations, the square root can be implemented as an instruction directly in the hardware, which improves the performance of the decimal floating-point unit in the processors. Hardware implementation of decimal square rooters is usually done using either functional or digit-recurrence algorithms. Functional algorithms, entailing multiplication per iteration, seem inadequate to use for decimal square roots, given the high cost of decimal multipliers. On the other hand, digit-recurrence square root algorithms, particularly SRT (this method is named after its creators, Sweeney, Robertson, and Tocher) algorithms, are simple and well suited for decimal arithmetic. This paper, with the intention of reducing the latency of the decimal square root operation while maintaining a reasonable cost, proposes an SRT algorithm and the corresponding hardware architecture to compute the decimal square root. The proposed fixed-point square root design requires n+3 cycles to compute an n-digit root; the synthesis results show an area cost of about 31K NAND2 and a cycle time of 40 FO4. These results reveal the 14 % speed advantage of the proposed decimal square root architecture over the fastest previous work (which uses a functional algorithm) with about a quarter of the area.     

Pixel‐Structured Scintillator with Polymeric Microstructures for X‐Ray Image Sensors

We introduce a pixel‐structured scintillator realized on a flexible polymeric substrate and demonstrate its feasibility as an X‐ray converter when it is coupled to photosensitive elements. The sample was prepared by filling Gd₂O₂S:Tb scintillation material into a square‐pore‐shape cavity array fabricated with polyethylene. For comparison, a sample with the conventional continuous geometry was also prepared. Although the pixelated geometry showed X‐ray sensitivity of about 58% compared with the conventional geometry, the resolving power was improved by about 70% above a spatial frequency of 3 mm^?1. The spatial frequency at 10% of the modulation‐transfer function was about 6 mm^?1.     

A traffic control system for IEEE 802.11 networks based on available bandwidth estimation

To support Quality of service (QoS)‐sensitive applications like real‐time video streaming in IEEE 802.11 networks, a MAC layer extension for QoS, IEEE 802.11e, has been recently ratified as a standard. This MAC layer solution, however, addresses only the issue of prioritized access to the wireless medium and leaves such issues as QoS guarantee and admission control to the traffic control systems at the higher layers. This paper presents an IP‐layer traffic control system for IEEE 802.11 networks based on available bandwidth estimation. We build an analytical model for estimating the available bandwidth by extending an existing throughput computation model, and implement a traffic control system that provides QoS guarantees and admission control by utilizing the estimated available bandwidth information. We have conducted extensive performance evaluation of the proposed scheme via both simulations and measurements in the real test‐bed. The experiment results show that our estimation model and traffic control system work accurately and effectively in various network load conditions without IEEE 802.11e. The presence of IEEE 802.11e will allow even more efficient QoS provision, as the proposed scheme and the MAC layer QoS support will complement each other. Copyright © 2006 John Wiley & Sons, Ltd.     

Distributed Multirobot Exploration and Mapping

Efficient exploration of unknown environments is a fundamental problem in mobile robotics. We present an approach to distributed multirobot mapping and exploration. Our system enables teams of robots to efficiently explore environments from different, unknown locations. In order to ensure consistency when combining their data into shared maps, the robots actively seek to verify their relative locations. Using shared maps, they coordinate their exploration strategies to maximize the efficiency of exploration. This system was evaluated under extremely realistic real-world conditions. An outside evaluation team found the system to be highly efficient and robust. The maps generated by our approach are consistently more accurate than those generated by manually measuring the locations and extensions of rooms and objects.     

A dry-patterned Cu(Mg) alloy film as a gate electrode in a thin-film transistor liquid crystal display

The annealing of a Cu(4.5at.%Mg)/SiO₂/Si structure in ambient O₂ at 10 mtorr and 300–500°C allows for the out-diffusion of the Mg to the Cu surface, forming a thin MgO (15 nm) layer on the surface. The surface MgO layer was patterned and successfully served as a hard mask for the subsequent dry etching of the underlying Mg-depleted Cu films using an O₂ plasma and hexafluoroacetylacetone (H(hfac)) chemistry. The resultant MgO/Cu structure, with a taper slope of about 30°, shows the feasibility of dry etching of Cu(Mg) alloy films using a surface MgO mask scheme. A dry-etched Cu(4.5at.%Mg) gate a-Si:H thin-film transistor (TFT) has a field-effect mobility of 0.86 cm²/Vs, a subthreshold swing of 1.08 V/dec, and a threshold voltage of 5.7 V. A novel process for the dry etching of Cu(Mg) alloy films that eliminates the use of a hard mask, such as Ti, and results in a reduction in the process steps is reported for the first time in this work.