A Signed Array Multiplier with Bypassing Logic

A low power digital signed array multiplier based on a 2-dimensional (2-D) bypassing technique is proposed in this work. When the horizontally (row) or the vertically (column) operand is zero, the corresponding bypassing cells skip redundant signal transitions to avoid unnecessary calculation to reduce power dissipation. An 8×8 signed multiplier using the 2-D bypassing technique is implemented on silicon using a standard 0.18 μm CMOS process to verify power reduction performance. The power-delay product of the proposed 8×8 signed array multiplier is measured to be 31.74 pJ at 166 MHz, which is significantly reduced in comparison with prior works.     

Controlled Synthesis of Fe<Subscript>3</Subscript>O<Subscript>4</Subscript>/Ag Core–Shell Composite Nanoparticles with High Electrical Conductivity

The presented method provides an easy processing route to synthesize Fe₃O₄/Ag core–shell composite nanoparticles. Their structures were characterized by x-ray diffraction and transmission electron microscopy. The average size of the Fe₃O₄ core and Ag shell was about 32.0 nm and 5.0 nm (or 28.0 nm), respectively. Furthermore, magnetic measurements showed that the composite nanoparticles exhibited typical superparamagnetic behavior, specific saturation magnetization of ca. 24.0 emu/g, and intrinsic coercivity of 106.0 Oe. At the same time, high conductivity (64.7 S/cm) of the composite nanoparticles was also observed. This method provides an opportunity to synthesize other core–shell (Fe₃O₄) nanoparticles in a single step.     

Static and dynamic photoinduced magnetic effects in yttrium-iron garnet lightly doped with barium ions

In yttrium-iron garnet lightly doped with barium, direct measurements of the photoinduced changes in magnetostrictive strains disagree with those in magnetostriction constants at 78–100 K. This is attributed to a considerable photoinduced modification of the initial state in this sample due to a redistribution of the charge (during illumination) between cations of the ferromagnetic octahedral sublattice. In the same sample, the temperature dependence of the photoinduced disaccomodation of magnetic permeability characterizing the initial demagnetized state is measured and calculated. A change in the electron mechanism of the phenomenon during the transition to room temperature is shown. The conclusion about the promising prospects for using such samples for remagnetization by light is advanced.     

Modified Shuffled Based Architecture for High-Throughput Decoding of LDPC Codes

Low Density Parity-Check (LDPC) codes achieve the best performance when they are decoded with the sum-product (SP) algorithm. This is a two-phase iterative algorithm where two types of messages are interchanged and updated in each iteration. The group-shuffled or layered decoding schemes applied to the SP algorithm speed up its convergence by modifying its schedule, so they yield a reduction in the number of iterations required to achieve a given performance. However, the two-phase processing is still maintained. In this paper a modification of the group-shuffled scheme suitable for high-rate LDPC codes is proposed. The modification allows the overlapping of the two-phase computation, achieving a convergence speed up close to that of the group-shuffled scheme with higher throughput. Besides, high throughput architectures are presented for the modified algorithm. As an example, the proposed architecture has been implemented for the 2048-bit LDPC code of the IEEE 802.3an standard and it was synthesized in a 90 nm CMOS process achieving a throughput of 22.40 Gbps at 14 iterations with a clock frequency of 306 MHz and a total area of 10.5 mm². Furthermore, the decoder performs within 0.5 dB of the floating-point 100 iterations sum-product algorithm at a PER of 10⁻⁵.     

Observation on Defects in Poly-Si Films Prepared by RTCVD Under Nonideal Conditions

Polycrystalline silicon (poly-Si) thin films were deposited on quartz substrates by rapid thermal chemical vapor deposition (RTCVD) under nonideal conditions. Then, crystallographic defects in the poly-Si films were investigated by using transmission electron microscopy (TEM) and optical microscopy combined with defect etching. We found that as-deposited poly-Si films contain a lot of twin crystals, including first-order, second-order, third-order, and higher-order twinned crystals. Besides twinned crystals, stacking faults, dislocations, dislocation nets, dislocation loops, extended dislocations, and dislocation line arrays were also found. Finally, the origins of the defects were analyzed, being attributed to the peculiarities of the RTCVD-quartz growth system, stress caused by lattice and thermal mismatch, a huge temperature ramp, and nonideal deposition conditions. Although our experimental results cannot represent the crystallographic quality of poly-Si films prepared by RTCVD, they at least indicate what kinds and how many defects exist in poly-Si films when deposition conditions severely deviate from the optimum.     

A 1.4GS/s 9-bit 45 dB power control RFDAC for digital radio transmitters

This paper presents a high speed, 9-bit RF Digital-to-Analog Converter based on a new architecture implemented in a 0.13 μm BiCMOS process and able to adjust the output power by 45 dB to meet gain control requirements of the new communications standards with a SFDR >25 dBc. The maximum test-demonstrated frequency is 1.4 GHz and the chip dissipates <25 mW.     

A 5.25-GHz low-power down-conversion mixer in 0.18-μm CMOS technology

A 5.25 GHz low voltage, high linear and isolated mixer using TSMC 0.18 μm CMOS process for WLAN receiver was investigated. The paper presents a novel topology mixer that leads to better performance in terms of linearity, isolation and power consumption for low supply voltage. The measuring results of the proposed mixer achieve: 7.6 dB power conversion gain, 11.4 dB double side band noise figure, 3 dBm input third-order intercept point, and the total dc power consumption of this mixer including output buffers is 2.45 mW from a 1 V supply voltage. The current output buffer is about 2 mW, the excellent LO-RF, LO-IF and RF-IF isolation achieved up to 37.8, 54.8 and 38.2 dB, respectively.     

Adaptive gain and delay mismatch cancellation for LINC transmitter

Linear amplification with Nonlinear Component (LINC) transmitter architecture is an efficient solution for high efficiency amplification of signals. Nonetheless, this solution suffers both from gain impairment and delay mismatch between the two signal paths. Indeed, a mismatch in propagation time between the paths degrades the quality of the transmit signal but also disrupts the convergence of the gain correction algorithm resulting in a degradation of its performance. In this paper, we present an adaptive algorithm based on a gradient descent formulation for the identification and correction of these delays. We also demonstrate its effectiveness when applied prior to the gain adjustment procedure. The identification approach is preferred here, to ensure monitoring facilities.     

Performance evaluation of fault-branch detection in TDM passive optical networks by spectral analysis of interferometric signals

A new fault-branch detection scheme is proposed to troubleshoot the breaks of any distribution fibers in a time-division multiplexing (TDM) passive optical network. We employ a continuous optical frequency sweeper at the optical line terminal (OLT) and an interferometric (IF) device at each optical network unit (ONU). By analyzing the spectrum of the returned combined signals at the OLT, we can obtain the status of all branches. This detection method not only uses a small optical frequency band for surveillance monitoring, but is also simple to operate. Furthermore, a modified architecture is proposed to relax the specifications of IF devices. The tolerance of the IF device length was analyzed using the Monte–Carlo simulation method.     

Total Power Optimization for Combinational Logic Using Genetic Algorithms

Power consumption is a top priority in high performance circuit design today. Many low power techniques have been proposed to tackle the ever serious, highly pressing power consumption problem, which is composed of both dynamic and static power in the nanometer era. The static power consumption nowadays receives even more attention than that of dynamic power consumption when technology scales below 100 nm. In order to mitigate the aggressive power consumption, various existing low power techniques are often used; however, they are often applied independently or combined with two or at most three different techniques together, and that is not sufficient to address the escalating power issue. In this paper, we present a power optimization framework for the minimization of total power consumption in combinational logic through multiple V _dd assignment, multiple V _th assignment, device sizing, and stack forcing, while maintaining performance requirements. These four power reduction techniques are properly encoded into the genetic algorithm and evaluated simultaneously. The overhead imposed by the insertion of level converters is also taken into account. The effectiveness of each power reduction mechanism is verified, as are the combinations of different approaches. Experimental results are presented for a number of 65 nm benchmark circuits that span typical circuit topologies, including inverter chains, SRAM decoders, multiplier, and a 32 bit carry adder. Our experiments show that the combination of four low power techniques is the effective way to achieve low power budget. The framework is general and can be easily extended to include other design-time low power techniques, such as multiple gate length or multiple gate oxide thickness.