On Faster I DDQ Measurements

The purpose of this paper is to introduce a new I _DDQ measurement technique based on active successive approximations, called ASA-I _DDQ. This technique has unique features facilitating a speed-up in I _DDQ measurement. Experimental results suggest that a significant speed-up factor (up to 4) can be obtained over the QuiC-Mon technique. Such a speed-up is a key element in the replacement of single-threshold I _DDQ testing since it amplifies the effectiveness of post-processing techniques.     

微制造平台微振动的最优控制

采用混合隔振技术建立了微制造平台隔振系统。该系统以空气弹簧和橡胶层作为被动隔振元件、超磁致伸缩致动器作为主动隔振元件，并采用最优控制理论设计其主动控制器。研究了在不同的性能指标加权阵的情况下，该主动振动控制系统对基础干扰和由微制造设备产生的直接干扰所引起的微制造平台振动的控制效果。研究表明性能指标加权阵对振动控制效果影响非常大。通过大量的仿真实验确定了一组性能指标加权阵，使所设计的主动控制系统能在较宽的频率范围对基础干扰和直接干扰所引起的微制造平台振动进行有效的控制。     

On-demand learning for a wireless campus

The current Internet and wireless networks are harsh environments for transporting high-bandwidth multimedia data. We examine the technical issues involved, and describe an end-to-end solution to support a Web-based learn-on-demand system that operates in a wireless campus environment.     

Radiometric sensor for temperature control of food processing

This paper describes a novel planar antenna sensor created for the purpose of noninvasive temperature measurements using microwave radiometry. In order to improve radiometric measurements in industrial applications, a new generation of sensors is introduced, composed of a metallic sheet. Simulations based upon the method of moments is used both to design and to determine their electromagnetic performances. This paper also describes a radiometric device using these sensors to measure and control the temperature of food products during deep freezing processes. The results and discussions are presented.     

Finite element analysis of advanced multilayer capacitors

We establish a systematic methodology to design and analyse electromagnetic components such as advanced multilayer ceramic capacitors (MLCCs) using the finite element (FE) method. We employ a coupled formulation to compute the interaction between the electric and magnetic fields. Unlike a linear distribution of current assumed in the circuit model, an accurate electrostatic solution to model the entire advanced MLCCs (4 × 4 × 27 = 432 cells) is presented. The FE solution is used to compute the lumped parameters for a range of frequencies. These lumped parameters are then used to compute the parasitic elements of the MLCCs. We introduce two algorithms to efficiently analyse the behaviour of a capacitor with changing frequency. The lower frequency (much below the self‐resonant frequency of the capacitor) algorithm separates the effect of the electric and magnetic fields and reduces the computational effort required to solve the FE problem, whereas, the high‐frequency algorithm couples the effect between the electric and the magnetic fields. We use these algorithms in conjunction with a new multiple scale technique to effectively determine the small values of R, L and C in MLCCs. The formulation, the implementation, and the numerical results demonstrate the efficacy of the present FE formulation and establish a systematic methodology to design and analyse advanced electromagnetic components. Copyright © 2003 John Wiley & Sons, Ltd.     

Exposed Die-Top Encapsulation Molding for an Improved High- Performance Flip Chip BGA Package

The recent advancement in high- performance semiconductor packages has been driven by the need for higher pin count and superior heat dissipation. A one-piece cavity lid flip chip ball grid array (BGA) package with high pin count and targeted reliability has emerged as a popular choice. The flip chip technology can accommodate an I/O count of more than five hundreds500, and the die junction temperature can be reduced to a minimum level by a metal heat spreader attachment. None the less, greater expectations on these high-performance packages arose such as better substrate real estate utilization for multiple chips, ease in handling for thinner core substrates, and improved board- level solder joint reliability. A new design of the flip chip BGA package has been looked into for meeting such requirements. By encapsulating the flip chip with molding compound leaving the die top exposed, a planar top surface can be formed. A, and a flat lid can then be mounted on the planar mold/die top surface. In this manner the direct interaction of the metal lid with the substrate can be removed. The new package is thus less rigid under thermal loading and solder joint reliability enhancement is expected. This paper discusses the process development of the new package and its advantages for improved solder joint fatigue life, and being a multichip package and thin core substrate options. Finite-element simulations have been employed for the study of its structural integrity, thermal, and electrical performances. Detailed package and board-level reliability test results will also be reported