Design of Engineered Elastomeric Substrate for Stretchable Active Devices and Sensors

In the field of flexible electronics, emerging applications require biocompatible and unobtrusive devices, which can withstand different modes of mechanical deformation and achieve low complexity in the fabrication process. Here, the fabrication of a mesa‐shaped elastomeric substrate, supporting thin‐film transistors (TFTs) and logic circuits (inverters), is reported. High‐relief structures are designed to minimize the strain experienced by the electronics, which are fabricated directly on the pillars' surface. In this design configuration, devices based on amorphous indium‐gallium‐zinc‐oxide can withstand different modes of deformation. Bending, stretching, and twisting experiments up to 6 mm radius, 20% uniaxial strain, and 180° global twisting, respectively, are performed to show stable electrical performance of the TFTs. Similarly, a fully integrated digital inverter is tested while stretched up to 20% elongation. As a proof of the versatility of mesa‐shaped geometry, a biocompatible and stretchable sensor for temperature mapping is also realized. Using pectin, which is a temperature‐sensitive material present in plant cells, the response of the sensor shows current modulation from 13 to 28 °C and functionality up to 15% strain. These results demonstrate the performance of highly flexible electronics for a broad variety of applications, including smart skin and health monitoring.     

Voltage refinement by deficit HOLZ line geometry

A method of refining electron beam voltage from deficit line intersections, using a quasi-kinematic scattering approximation, is described and applied to a silicon standard. It is shown that dynamical corrections are necessary for higher-index zone axes, such as 310 and 411, where a single deficit line associated with one dominant Bloch state is visible. This leads to a substantial difference in the refined voltage compared with that obtained from a purely kinematic approximation. Neglect of this dynamical correction term effectively invokes a systematic error that may lead to high precision but poor accuracy in higher-order Laue zone measurements of beam voltage or lattice parameters. Although relatively small, differences in the dynamical correction necessary for these two zones are confirmed experimentally for 100-300 keV electrons.     

Morphology Transformation Pathway of Block Copolymer-Directed Cooperative Self-Assembly of ZnO Hybrid Films Monitored In Situ during Slot-Die Coating

Cooperative self-assembly (co-assembly) of diblock copolymers (DBCs) and inorganic precursors that takes inspiration from the rich phase separation behavior of DBCs can enable the realization of a broad spectrum of functional nanostructures with the desired sizes. In a DBC assisted sol–gel chemistry approach with polystyrene-block-poly(ethylene oxide) and ZnO, hybrid films are formed with slot-die coating. Pure DBC films are printed as control. In situ grazing-incidence small-angle X-ray scattering measurements are performed to investigate the self-assembly and co-assembly process during the film formation. Combining complementary ex situ characterizations, several distinct regimes are differentiated to describe the morphological transformations from the initially solvent-dispersed to the ultimately solidified films. The comparison of the assembly pathway evidences that the key step in the establishment of the pure DBC film is the coalescence of spherical micelles toward cylindrical domains. Due to the presence of the phase-selective precursor, the formation of cylindrical aggregates in the solution is crucial for the structural development of the hybrid film. The pre-existing cylinders in the ink impede the domain growth of the hybrid film during the subsequent drying process. The precursor reduces the degree of order, prevents crystallization of the PEO block, and introduces additional length scales in the hybrid films.     

Still Image Processing on Coarse-Grained Reconfigurable Array Architectures

Due to the increasing demands on efficiency, performance and flexibility reconfigurable computational architectures are very promising candidates in embedded systems design. Recently coarse-grained reconfigurable array architectures (CGRAs), such as the ADRES CGRA and its corresponding DRESC compiler are gaining more popularity due to several technological breakthroughs in this area. We investigate the mapping of two image processing algorithms, Wavelet encoding and decoding, and TIFF compression on this novel type of array architectures in a systematic way. The results of our experiments show that CGRAs based on ADRES and its DRESC compiler technology deliver improved performance levels for these two benchmark applications when compared to results obtained on a state-of-the-art commercial DSP platform, the c64x DSP from Texas Instruments. ADRES/DRESC can beat its performance by at least 50% in cycle count and the power consumption even drops to 10% of the published numbers of the c64x DSP.     

Caractérisation et résultats de fiabilité de transistors à haute mobilité électronique (HEMT)

The telecommunication systems require introduction of high performance devices especially for microwave applications. The emergence of molecular beam epitaxy as a growth technique allows the fabrication of heterostructure-based performing devices. Thus, this communication will focus on the reliability of technologies used for the development of field effect transistor using heterostructures and called HEMT (high electron mobility transistor).     

An analytic method to predict the thermal map of cryosurgery iceballs in MR images

This paper presents a newly developed method to estimate, in magnetic resonance (MR) images, the temperatures reached within the volume of an iceball produced by a cryogenic probe. Building on the direct measurements of the MR signal intensity and its correlation with independent temperature variations at the phase transition from liquid to solid, the thermal information embedded in the images was accessed. The volume and diameter of the growing iceball were estimated from a time series of MR images. Using regressions over the volume in the time and thermal domains, this method predicted the cryogenic temperatures beyond the range of sensitivity of the MR signal itself. We present a validation of this method in samples of gelatin and ex vivo pig liver. Temperature predictions are shown to agree with independent thermosensor readings over a range extending from 20 degrees C down to -65 degrees C, with an average error of less than 6 degrees C.     

A Memristive Nanoparticle/Organic Hybrid Synapstor for Neuroinspired Computing

A large effort is devoted to the research of new computing paradigms associated with innovative nanotechnologies that should complement and/or propose alternative solutions to the classical Von Neumann/CMOS (complementary metal oxide semiconductor) association. Among various propositions, spiking neural network (SNN) seems a valid candidate. i) In terms of functions, SNN using relative spike timing for information coding are deemed to be the most effective at taking inspiration from the brain to allow fast and efficient processing of information for complex tasks in recognition or classification. ii) In terms of technology, SNN may be able to benefit the most from nanodevices because SNN architectures are intrinsically tolerant to defective devices and performance variability. Here, spike‐timing‐dependent plasticity (STDP), a basic and primordial learning function in the brain, is demonstrated with a new class of synapstor (synapse‐transistor), called nanoparticle organic memory field‐effect transistor (NOMFET). This learning function is obtained with a simple hybrid material made of the self‐assembly of gold nanoparticles and organic semiconductor thin films. Beyond mimicking biological synapses, it is also demonstrated how the shape of the applied spikes can tailor the STDP learning function. Moreover, the experiments and modeling show that this synapstor is a memristive device. Finally, these synapstors are successfully coupled with a CMOS platform emulating the pre‐ and postsynaptic neurons, and a behavioral macromodel is developed on usual device simulator.