Trenched‐Sinker LDMOSFET (TS‐LDMOS) Structure for 2 GHz Power Amplifiers

This paper proposes a new LDMOSFET structure with a trenched sinker for high‐power RF amplifiers. Using a low‐temperature, deep‐trench technology, we succeeded in drastically shrinking the sinker area to one‐third the size of the conventional diffusion‐type structure. The RF performance of the proposed device with a channel width of 5 mm showed a small signal gain of 16.5 dB and a maximum peak power of 32 dBm with a power‐added efficiency of 25% at 2 GHz. Furthermore, the trench sinker, which was applied to the guard ring to suppress coupling between inductors, showed an excellent blocking performance below ?40 dB at a frequency of up to 20 GHz. These results confirm that the proposed trenched sinker should be an effective technology both as a compact sinker for RF power devices and as a guard ring against coupling.     

CDT进军P-OLED市场

发光聚合物P-OLED开发领导厂商并将P-OLED广泛应用在电子显示器产品上的剑桥显示技术公司(CDT),是一家于1992年在英国成立,以发展、制造并销售P-OLED材料与IP给显示器产业的公司。P-OLED隶属于有机发光二极管的一部份,是一种质地薄、重量轻且具功率效益的组件,当电流流过时就会发光。相较于其它平面显示器技术,如液晶显示器,它们提供更为强化的视觉体验与卓越的效能特性。在技术方面,2005年计有9家获授权公司给付权利金,授权金额总计达到420万美元。这些授权的客户包括Epson在内,Epson最近才发表一项使用OLED做为高亮度的光源,…     

Data retention characteristics of sub-100 nm NAND flash memory cells

In contrast to the conventional theories, we have revealed that the most distinguished mechanism in the data retention phenomenon after Fowler-Nordheim (FN) stress in sub-100 nm NAND Flash memory cells is the annihilation of interface states. Interface state generation rate increases rapidly as the channel width of NAND flash cell decreases. Comparison of interface states and stress-induced leakage current (SILC) component during retention mode shows that the annihilation of interface states strongly affects data retention characteristics of the programmed cells.     

Vortex Dynamics in Bi2Sr2CaCu2O8 Single Crystal with Low Density Columnar Defects Studied by Magnetic Force Microscope

We have studied vortex dynamics in Bi₂Sr₂CaCu₂O₈ single crystal with low density columnar defects by using a magnetic force microscope. Single crystal Bi₂Sr₂CaCu₂O₈ sample was irradiated by 1.3 GeV uranium ion to form artificial pinning centers along the crystalline c-axis. The irradiation dose corresponded to a matching field of 20 gauss. The radius of an individual vortex is approximately 140 nm, which is close to the penetration depth of this material. Magnetic force microscope (MFM) images show that intrinsic crystalline defects such as stacking fault dislocations are very effective pinning centers for vortices in addition to the pinning centers due to ion bombardment. By counting the number of vortex, we found that the flux trapped at each pinning center is a single flux quantum. At higher magnetic field, the vortex structure showed an Abrikosov lattice disturbed only by immobile vortices located at pinning centers. When increasing or decreasing the external magnetic field, the spatial distribution of vortices showed a Bean model like behavior.     

Presenting information on the small-screen interface: effects of table formatting

This study explored strengths and limitations of table formatting choices by engaging twenty-eight participants in information searches in online tables, presented on a small-screen interface (Palm IIIc). Table length across conditions was held constant at three screens long (24 rows total) but varied from one to three screens wide (approximately 35, 70, and 105 characters per line). Target information was positioned in either the upper left, lower left, upper right, or lower right quadrants. Data collected were time on task, error rate, and level of participants' confidence in their answers. Experimenters found that increased horizontal scrolling imposed the heaviest burden on information search. This study supports restricting table widths to one screen on handheld computers. If necessary, however, tables can go to two screens wide without critical detriment to usability. While ruled line formatting is slightly better than interface character in providing visual support for the burden of horizontal scrolling, neither formatting option adequately compensates for the added burden.     

Origin of the threshold voltage instability in SiO/sub 2//HfO/sub 2/ dual layer gate dielectrics

The magnitude of the V/sub T/ instability in conventional MOSFETs and MOS capacitors with SiO/sub 2//HfO/sub 2/ dual-layer gate dielectrics is shown to depend strongly on the details of the measurement sequence used. By applying time-resolved measurements (capacitance-time traces and charge-pumping measurements), it is demonstrated that this behavior is caused by the fast charging and discharging of preexisting defects near the SiO/sub 2//HfO/sub 2/ interface and in the bulk of the HfO/sub 2/ layer. Based on these results, a simple defect model is proposed that can explain the complex behavior of the V/sub T/ instability in terms of structural defects as follows. 1) A defect band in the HfO/sub 2/ layer is located in energy above the Si conduction band edge. 2) The defect band shifts rapidly in energy with respect to the Fermi level in the Si substrate as the gate bias is varied. 3) The rapid energy shifts allows for efficient charging and discharging of the defects near the SiO/sub 2//HfO/sub 2/ interface by tunneling.     

Effect of exponentially graded base doping on the performance ofGaAs/AlGaAs heterojunction bipolar transistors

The authors have fabricated n-p-n GaAs/AlGaAs heterojunction bipolar transistors (HBTs) with base doping graded exponentially from 5×10¹⁹ cm^-3 at the emitter edge to 5×10¹⁸ cm^-3 at the collector edge. The built-in field due to the exponentially graded doping profile significantly reduces base transit time, despite bandgap narrowing associated with high base doping. Compared to devices with the same base thickness and uniform base doping of 1×10¹⁹ cm^-3 , the cutoff frequency is increased from 22 to 31 GHz and maximum frequency of oscillation is increased from 40 to 58 GHz. Exponentially graded base doping also results ill consistently higher common-emitter current gain than uniform base doping, even though the Gummel number is twice as high and the base resistance is reduced by 40%     

Rotative quadrature phase-shift keying

A rotative quadrature phase-shift keying (RQPSK) modulation scheme is proposed. By rotating the QPSK signal constellation by pi /2 either clockwise or anticlockwise during a symbol duration, the conventional QPSK scheme can be modified to transmit 3 bits per symbol to achieve both power and bandwidth efficiency.<>     

89-GHz fT room-temperature silicon MOSFETs

The authors report the implementation of deep-submicrometer Si MOSFETs that at room temperature have a unity-current-gain cutoff frequency (f_T) of 89 GHz, for a drain-to-source bias of 1.5 V, a gate-to-source bias of 1 V, a gate oxide thickness of 40 Å, and a channel length of 0.15 μm. The fabrication procedure is mostly conventional, except for the e-beam defined gates. The speed performance is achieved through an intrinsic transit time of only 1.8 ps across the active device region     

A practical SPICE model based on the physics and characteristics of realistic single-electron transistors

A practical model for a single-electron transistor (SET) was developed based on the physical phenomena in realistic Si SETs, and implemented into a conventional circuit simulator. In the proposed model, the SET current calculated by the analytic model is combined with the parasitic MOSFET characteristics, which have been observed in many recently reported SETs formed on Si nanostructures. The SPICE simulation results were compared with the measured characteristics of the Si SETs. In terms of the bias, temperature, and size dependence of the realistic SET characteristics, an extensive comparison leads to good agreement within a reasonable level of accuracy. This result is noticeable in that a single set of model parameters was used, while considering divergent physical phenomena such as the parasitic MOSFET, the Coulomb oscillation phase shift, and the tunneling resistance modulated by the gate bias. When compared to the measured data, the accuracy of the voltage transfer characteristics of a single-electron inverter obtained from the SPICE simulation was within 15%. This new SPICE model can be applied to estimating the realistic performance of a CMOS/SET hybrid circuit or various SET logic architectures.