Fatty diet and multiple sclerosis]

INTRODUCTION AND DEVELOPMENT: Multiple sclerosis (ME) is an inflammatory disease of the myelin of the central nervous system, the origin of which is still unknown. Genetic, infectious, immunological and environmental factors have all been blamed, but none of these factors on their own can explain the whole spectrum of this disease. Of the environmental factors, fat in the diet has given rise to most discussion. At the present time, it is known that polyunsaturated essential fatty acids form a part of biological membranes. A relationship has been found between the dietary fat consumed and the plasma levels and cell membrane content. CONCLUSIONS: The possible immuno-modulation function of these fatty acids justify rigorous evaluation of this hypothesis.     

Predominant expression of monoamine oxidase B isoform in rabbit renal proximal tubule: regulation by I2 imidazoline ligands in intact cells

Previous studies have shown that a subpopulation of the catecholamine-degrading enzymes monoamine oxidase (MAO) A and B holds a previously unknown regulatory site, the I2-imidazoline binding site (I2BS). In the present work, we characterized the isoforms of monoamine oxidases expressed in the rabbit renal proximal tubule, defined their relationship with I2BS, and investigated the ability of I2BS ligands to inhibit enzyme activity in intact cells. Two findings indicate that MAO-B is the predominant isoform expressed in the renal proximal tubule cells: 1) Western blot performed with an anti-MAO-A/MAO-B polyclonal antiserum revealed a single 55-kDa band corresponding to MAO-B; 2) enzyme assays showed an elevated MAO-B activity ([14C]beta-phenylethylamine oxidation: Vmax = 1.31 +/- 0.41 nmol/min/mg protein), whereas MAO-A activity was only detectable ([14C]5-HT oxidation: Vmax = 80.3 +/- 19 pmol/min/mg protein). Photoaffinity labeling with the I2BS ligand [125I]2-(3-azido-4-iodophenoxy)-methylimidazoline revealed a single 55-kDa band, which indicates that MAO-B of the renal proximal tubule cells holds the I2 imidazoline binding site. [3H]Idazoxan binding studies and enzyme assays showed that, in intact cells, I2BS ligands bind to and inhibit MAO-B. Indeed, the increase in the accessibility of intracellular compartment by cell permeabilization did not enhance [3H]idazoxan binding, which indicates that, in intact cells, intracellular I2BS are fully occupied by imidazoline ligands. In addition, enzyme assays showed that incubation of proximal tubule cells with imidazoline ligands leads to a complete, dose-dependent inhibition of MAO activity. These data show the predominant expression of MAO-B in rabbit renal proximal tubule and its regulation by imidazoline ligands in intact cells.     

Simultaneous design of power stage and controller for switchingpower supplies

This paper develops a method for simultaneously designing the power stage and controller for a switching power supply. The method utilizes a numerical optimization procedure, which facilitates computer-aided design. It is found that better performance can be achieved than with a traditional two-step design process, where the power stage and controller are designed sequentially. Optimization and simulation results for a buck power converter are presented to illustrate the design process and benefits     

Optimal detection of visual evoked potentials

The authors consider the problem of detecting visual evoked potentials (VEP's). A matched subspace filter is applied to the detection of the VEP and is demonstrated to perform better than a number of other evoked potential detectors. Unlike single-harmonic detectors, the matched subspace filter (MSF) detector is suitable for detecting multiharmonic VEP's. Moreover, the MSF is optimal in the uniformly most powerful sense for multiharmonic signals with unknown noise variance     

Performance of interface engineeredSiNx/ICL/InP/In0.53Ga0.47As/InP dopedchannel HIGFET's

SiN_x/InP/InGaAs doped channel passivated heterojunction insulated gate field effect transistors (HIGFETs) have been fabricated for the first time using an improved In-S interface control layer (ICL). The insulated gate HIGFETs exhibit very low gate leakage (10 nA@V_GS =±5 V) and I_DS (sat) of 250 mA/mm. The doped channel improves the DC characteristics and the HIGFETs show transconductance of 140-150 mS/mm (L_g=2 μm), f_t of 5-6 GHz (L_g=3 μm), and power gain of 14.2 dB at 3 GHz. The ICL HIGFET technology is promising for high frequency applications     

Parallel reduced area multipliers

As developed by Wallace and Dadda, a method for high-speed, parallel multiplication is to generate a matrix of partial products and then reduce the partial products to two numbers whose sum is equal to the final product. The resulting two numbers are then summed using a fast carry-propagate adder. This paper presents Reduced Area multipliers, which employ a modified reduction scheme that results in fewer components and less interconnect overhead than either Wallace or Dadda multipliers. This reduction scheme is especially useful for pipelined multipliers, because it minimizes the number of latches required in the reduction of the partial products. The reduction scheme can be applied to either unsigned (sign-magnitude) or two's complement numbers. Equations are given for determining the number of components and a method is presented for estimating the interconnect overhead for Wallace, Dadda, and Reduced Area multipliers. Area estimates indicate that for non-pipelined multipliers, the reduction in area achieved with Reduced Area multipliers ranges from 3.7 to 6.6 percent relative to Dadda multipliers, and from 3.8 to 8.4 percent relative to Wallace multipliers. For fully pipelined multipliers, the reduction in area ranges from 15.1 to 33.6 percent relative to Dadda multipliers, and from 2.9 to 9.0 percent relative to Wallace multipliers.     

Threshold voltage-minimum gate length trade-off in buried channelPMOS devices for scaled supply voltage CMOS technologies

The trade-off between threshold voltage (V_th) and the minimum gate length (L_min) is discussed for optimizing the performance of buried channel PMOS transistors for low voltage/low power high-speed digital CMOS circuits. In a low supply voltage CMOS technology it is desirable to scale V_th and L_min for improved circuit performance. However, these two parameters cannot be scaled independently due to the channel punch-through effect. Statistical process/device modeling, split lot experiments, circuit simulations, and measurements are performed to optimize the PMOS transistor current drive and CMOS circuit speed. We show that trading PMOS transistor V_th for a smaller L_min results in faster circuits for low supply voltage (3.3 to 1.8 V) n⁺-polysilicon gate CMOS technology, Circuit simulation and measurements are performed in this study. Approximate empirical expressions are given for the optimum buried channel PMOS transistor V _th for minimizing CMOS circuit speed for cases involving: (1) constant capacitive load and (2) load capacitance proportional to MOS gate capacitance. The results of the numerical exercise are applied to the centering of device parameters of a 0.5 μm 3.3 V CMOS technology that (a) matches the speed of our 0.5 μm 5 V CMOS technology, and (b) achieves good performance down to 1.8 V power supply. For this process the optimum PMOS transistor V_th (absolute value) is approximately 0.85-0.90 V