Improvement of inductive power collection in null-flux maglev system

In the superconducting maglev system it is important to develop a non-contact on-board power source without environmental pollution such as noise and exhaust gases; therefore, inductive power collection (IPC), which utilizes a harmonic magnetic field generated by ground coils in EDS, is being studied. However, alteration to a null-flux EDS that has a high drag ratio reduces the power collecting capacity in the IPC system. In addition, power collecting coils are located on the cryostat of the superconducting coil (SC), so eddy currents at the cryostat also reduce the power collecting capacity. Therefore, an exclusive SC type that locates the exclusive SCs and IPC and power collecting coils so as to face the upper and lower coils of ground coils, respectively, is examined; but we aim to improve the conventional type. After analyzing the influence of eddy currents at the cryostat in detail and improving the composition of the power collecting coil and cryostat, we found that the conventional type has the same capacity as the exclusive SC type. In order to prove the above-mentioned result, we measured the induced voltage of the new-type coils in a test run at Miyazaki test track and confirmed the output of this IPC system in a full-scale synthetic bench test with a PWM converter and magnetic field simulator. © 1998 Scripta Technica. Electr Eng Jpn, 122(2): 48–60, 1998     

A real-time motion estimation and compensation LSI with wide searchrange for MPEG2 video encoding

This paper presents a motion estimation and compensation large scale integration (LSI) for the MPEG2 standard. An embedded RISC processor and special hardware modules enable the LSI to achieve a sufficient ability to perform real-time operation and provide the availability to realize many kinds of block matching algorithms. Using a three-step hierarchical telescopic search algorithm, a single chip accomplishes real-time motion estimation with search ranges of ±32.5×±32.5 pixels for motion vectors. The chip was fabricated using 0.5-μm CMOS technology and has an area of 16.5×16.5 mm² and 2.0 M transistors     

A 286 mm2 256 Mb DRAM with ×32 both-ends DQ

This paper describes a 256 Mb DRAM chip architecture which provides up to ×32 wide organization. In order to minimize the die size, three new techniques: an exchangeable hierarchical data line structure, an irregular sense amp layout, and a split address bus with local redrive scheme in the both-ends DQ were introduced. A chip has been developed based on the architecture with 0.25 μm CMOS technology. The chip measures 13.25 mm×21.55 mm, which is the smallest 256 Mb DRAM ever reported. A row address strobe (RAS) access time of 26 ns was obtained under 2.8 V power supply and 85°C. In addition, a 100 MHz×32 page mode operation, namely 400 M byte/s data rate, in the standard extended data output (EDO) cycle has been successfully demonstrated     

An experimental 1.5-V 64-Mb DRAM

Low-voltage circuit technologies for higher-density dynamic RAMs (DRAMs) and their application to an experimental 64-Mb DRAM with a 1.5-V internal operating voltage are presented. A complementary current sensing scheme is proposed to reduce data transmission delay. A speed improvement of 20 ns was achieved when utilizing a 1.5-V power supply. An accurate and speed-enhanced half-V_CC voltage generator with a current-mirror amplifier and tri-state buffer is proposed. With it, a response time reduction of about 1.5 decades was realized. A word-line driver with a charge-pump circuit was developed to achieve a high boost ratio. A ratio of about 1.8 was obtained from a power supply voltage as low as 1.0 V. A 1.28 μm² crown-shaped stacked-capacitor (CROWN) cell was also made to ensure a sufficient storage charge and to minimize data-line interference noise. An experimental 1.5 V 64 Mb DRAM was designed and fabricated with these technologies and 0.3 μm electron-beam lithography. A typical access time of 70 ns was obtained, and a further reduction of 50 ns is expected based on simulation results. Thus, a high-speed performance, comparable to that of 16-Mb DRAMs, can be achieved with a typical power dissipation of 44 mW, one tenth that of 16-Mb DRAMs. This indicates that a low-voltage battery operation is a promising target for future DRAMs     

High repetition rate, wide-aperture KrF lasers for subpicosecondamplification

A high repetition rate, wide-aperture KrF laser with a magnetic switch has been developed. A dynamic response and a core loss of several magnetic materials were measured, resulting in a loss as low as 0.45 J/pulse for a voltage risetime of ~100 ns. A maximum output energy of 2.5 J in 20 ns (FWHM) was obtained with a total efficiency of 2.5% at 20 Hz. The cross section of the output beam was 65×50 mm². Spectral, spatial, and temporal profiles of gain and absorption coefficients were also measured, resulting in a peak gain of 8.5%/cm. An output energy of 410 mJ was extracted in 280 fs with two beams by using this laser as an amplifier     

All solid-state battery with sulfur electrode and thio-LISICON electrolyte

A high-capacity type of all solid-state battery was developed using sulfur electrode and the thio-LISICON electrolyte. New nano-composite of sulfur and acetylene black (AB) with an average particle size of 1–10 nm was fabricated by gas-phase mixing and showed a reversible capacity of 900 mAh g⁻¹ at a current density of 0.013 mA cm⁻².     

A 99-mm2 0.7-W single-chip MPEG-2 422P@ML video, audio,and system encoder with a 64-Mb embedded DRAM for portable 422P@HLencoder system

A scalable single-chip 422P@ML MPEG-2 video, audio, and system encoder LSI for portable 422P@HL system is described. The encoder LSI is implemented using 0.13-μm embedded DRAM technology. It integrates 3-M logic gates and 64-Mb DRAM in an area of 99-mm². The power consumption is suppressed to 0.7 W by adopting a low-power DRAM core. It performs real-time 422P@ML video encoding, audio encoding, and system encoding with no external DRAM. Furthermore, the encoder LSI realizes a 422P@HL video encoder with multichip configuration, due to its scalable architecture. This results in a PC-card size 422P@HL encoder for portable HDTV codec system     

Bias-stress-induced increase in parasitic resistance of InP-based InAlAs/InGaAs HEMTs

The reliability of InP-based HEMTs is studied, focussing on how it is affected by the doped layer material and gate recess structure. Bias-and-temperature stress tests reveal that fluorine-induced donor passivation in the recess region, formed adjacent to the gate electrode, causes the source resistance (R_s) to increase at large drain bias voltages. The increase in R_s can be prevented by using InP or InAlP as the carrier supply layer material instead of InAlAs. On the other hand, the increase in the drain resistance (R_d) does not depend on the material of the carrier supply layer, which suggests that a mechanism different from that in the case of R_s should be considered. It is also found that a deep gate recess suppresses the increase in R_d after long-term stressing.     

Liquid Marble Patchwork on Super-Repellent Surface

Liquid marble (LM) is a droplet that is wrapped by hydrophobic solid particles, which behave as a non-wetting soft solid. Based on these properties, LM can be applied in fluidics and soft device applications. A wide variety of functional particles have been synthesized to form functional LMs. However, the formation of multifunctional LMs by integrating several types of functional particles is challenging. Here, a general strategy for the flexible patterning of functional particles on droplet surfaces in a patchwork-like design is reported. It is shown that LMs can switch their macroscopic behavior between a stable and active state on super-repellent surfaces in situ by jamming/unjamming the surface particles. Active LMs hydrostatically coalesce to form a self-sorted particle pattern on the droplet surface. With the support of LM handling robotics, on-demand cyclic activation–manipulation–coalescence–stabilization protocols by LMs with different sizes and particle types result in the reliable design of multi-faced LMs. Based on this concept, a single bi-functional LM is designed from two mono-functional LMs as an advanced droplet carrier.     

Photoactive Electro-Controlled Visual Perception Memory for Emulating Synaptic Metaplasticity and Hebbian Learning

In bionic technology, it has become an innovative process imitating the functionality and structuralism of human biological systems to exploit advanced artificial intelligent machines. Bionics plays a significant role in environmental protection, especially for its low energy loss. By fusing the concept of receptor-like sensing component and synapse-like memory, the photoactive electro-controlled optical sensory memory (PE-SM) is proposed and realized in a single device, which endows a simple methodology of reducing power consumption by photoactive electro-control. The PE-SM is the system built with the stacked atomically thick materials, in which rhenium diselenide serves as a robust photosensor, hexagonal boron nitride serves as a tunneling dielectric, and graphene serves as a charge-storage layer. With the features of the PE-SM, it performs synaptic metaplasticities under optical spikes. In addition, a simulated spiking neural network composed of 24 × 24 PE-SMs is further presented in an unsupervised machine learning environment, performing image recognition via the Hebbian rule. The PE-SM not only improves the neuromorphic computing efficiency but also simplifies the circuit-size structure. Eventually, the concept of photoactive electro-control can extend to other photosensitive 2D materials and provide a new approach of constructing either visual perception memory or photonic synaptic devices.