Volatile profile of Stilton cheeses: Differences between zones within a cheese and dairies

Penicillium roqueforti grows and sporulates during the ripening period of blue cheeses and it is responsible for the typical blue cheese flavour formation. However, the sporulation (blue veins) is taking place in a fraction of the total mass and the cheese matrix is highly heterogeneous. The aroma profiles regarding the three different sections of Stilton cheese, blue veins outer crust and white core, were studied using solvent extraction GC–MS, a headspace GC–MS technique (SPME GC–MS) and direct headspace analysis (APCI–MS). Cheeses from different dairies were analysed, allowing the question of how similar are different batches of cheese from different dairies.     

Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors

The continuous increase of the computational power of programmable processors has established them as an attractive design alternative, for implementation of the most computationally intensive applications, like video compression. To enforce this trend, designers implementing applications on programmable platforms have to be provided with reliable and in-depth data and instruction analysis that will allow for the early selection of the most appropriate application for a given set of specifications. To address this need, we introduce a new methodology for early and accurate estimation of the number of instructions required for the execution of an application, together with the number of data memory transfers on a programmable processor. The high-level estimation is achieved by a series of mathematical formulas; these describe not only the arithmetic operations of an application, but also its control and addressing operations, if it is executed on a programmable core. The comparative study, which is done using three popular processors (ARM, MIPS, and Pentium), shows the high efficiency and accuracy of the methodology proposed, in terms of the number of executed (micro-)instructions (i.e. performance) and the number of data memory transfers (i.e. memory power consumption). Using the proposed methodology we estimated an average deviation of 23% in our estimated figures compared with the measurements taken from the real execution on the CPUs. This work was supported by the project PENED ’99 ED501 funded by GSRT of the Greek Ministry of Development, and the project PRENED ’99 KE 874 funded by the Research Committee of the Democritus University of Thrace. This work was partially sponsored by a scholarship from the Public Benefit Foundation of Alexander S. Onassis (Minas Dasygenis). Nikolaos Kroupis was born in Trikala in 1976. He receiver the engineering degree and Ms.C. degree in Department of Electrical and Computer Engineering from Democritous University of Thrace, Greece, in 2000 and 2002, respectively. Since 2002 he has been a Ph.D. student at the Laboratory of Electrical and Electronic Materials Technology. His research interests are in software/hardware co-design of embedded system for signal processing applications. Nikos D. Zervas received a Diploma in Electrical & Computer Engineering from University of Patras, Greece in 1997. He received the Ph.D. degree in the Department of Electrical and Computer Engineering of the same University in 2004. His research interests are in the area of high-level, power optimization techniques and methodologies for multimedia and telecommunication applications. He has received an award from IEEE Computer Society in the context of Low-Power Design Contest of 2000 IEEE Computer Elements Mesa Workshop. Mr. Zervas is a member of the IEEE, ACM and of the Technical Chamber of Greece. Minas Dasygenis was born in Thessaloniki in 1976. He received his Diploma in Electrical and Computer Engineering in 1999, from the Democritus University of Thrace, Greece, and for his diploma Thesis he was honored by The Technical Chamber of Greece and Ericsson Hellas. In 2005, he received his PhD Degree from the Democritus University of Thrace. His research interests include low-power VLSI design of arithmetic circuits, residue number system, embedded architectures, DSPs, hardware/ software codesign and IT security. He has published more than 20 papers in international journals and conferences and he has been a principal researcher in three European research projects. Konstantinos Tatas received his degree in Electrical and Computer Engineering from the Democritus University of Thrace, Greece in 1999. He received his Ph.D. in the VLSI Design and Testing Center in the same University by June 2005. He has been employed as an RTL designer in INTRACOM SA, Greece between 2000 and 2003. His research interests include low-power VLSI design of DSP and multimedia systems, computer arithmetic, IP core design and design for reuse. Antonios Argyriou received the degree in Electrical and Computer engineering from the Democritous University of Thrace, Greece, in 2001, and the M.S. and Ph.D. degrees in Electrical and Computer engineering from the Georgia Institute of Technology, Atlanta, in 2003 and 2005, respectively. His primary research interests include wireless networks, mobile computing and multimedia communications. He is a member of the IEEE and ACM. Dimitrios Soudris received his Diploma in Electrical Engineering from the University of Patras, Greece, in 1987. He received the Ph.D. Degree in Electrical Engineering, from the University of Patras in 1992. He is currently working as Ass. Professor in Dept. of Electrical and Computer Engineering, Democritus University of Thrace, Greece. His research interests include low power design, parallel architectures, embedded systems design, and VLSI signal processing. He has published more than 140 papers in international journals and conferences. He was leader and principal investigator in numerous research projects funded from the Greek Government and Industry as well as the European Commission (ESPRIT II-III-IV and 5th and 6th IST). He has served as General Chair and Program Chair for the International Workshop on Power and Timing Modelling, Optimisation, and Simulation (PATMOS). He received an award from INTEL and IBM for the project results of LPGD #25256 (ESPRIT IV). He is a member of the IEEE, the VLSI Systems and Applications Technical Committee of IEEE CAS and the ACM. Antonios Thanailakis was born in Greece on August 5, 1940. He received B.Sc. degrees in physics and electrical engineering from the University of Thessaloniki, Greece, 1964 and 1968, respectively, and the Msc. and Ph.D. Degrees in electrical engineering and electronics from UMIST, Manchester, U.K. in 1968 and 1971, respectively. He has been a Professor of Microelectronics in Dept. of Electrical and Computer Eng., Democritus Univ. of Thrace, Xanthi, Greece, since 1977. He has been active in electronic device and VLSI system design research since 1968. His current research activities include microelectronic devices and VLSI systems design. He has published a great number of scientific and technical papers, as well as five textbooks. He was leader for carrying out research and development projects funded by Greece, EU, or other organizations on various topics of Microlectronics and VLSI Systems Design (e.g. NATO, ESPRIT, ACTS, STRIDE).     

Cost and Land Functions for Wastewater Treatment Projects: Typical Simple Linear Regression versus Fuzzy Linear Regression

This paper analyzes cost data pertinent to the municipal wastewater treatment plants (MWTP) in Greece. First, data have been collected with onsite visits and contain the land size necessary for a MWTP, the construction cost, and the operation and maintenance cost of existing wastewater treatment facilities. Second, they come from analytical budgeting of natural wastewater treatment system units. Twelve equations of the form ln?Yi = A0i+A1i?ln?Xi are estimated both with ordinary least squares (OLS) and fuzzy linear regression (FLR). The root mean square error and the mean absolute error are used as fitting measures for the comparison of the OLS with the fuzzy estimations. It is shown that the FLR did produce very similar estimates but slightly inferior to those of OLS in most of the cases for these particular datasets.     

CMOS weak‐inversion log‐domain glycolytic oscillator: a cytomimetic circuit example

This paper presents a 3 V, 1.21μW subthreshold log‐domain circuit which mimics the oscillations observed during the biochemical process of glycolysis due to the phosphofructokinase enzyme. The proposed electronic circuit is able to simulate the dynamics of the glycolytic oscillator and represent the time‐dependent concentration changes of the reactants and the products of the chemical process based on nonlinear differential equations which describe the biological system. By modifying specific circuit parameters, which correspond to certain chemical parameters, good agreement between the biochemical and electrical model results has been reached. The paper details the similarities between the equations that describe the biochemical process and the equations derived from the circuit analysis of a transistor and a source‐connected linear capacitor, a topology also known as the Bernoulli Cell. With the use of the Bernoulli Cell formalism, the chemical equations which describe the biochemical system have been transformed into their electrical equivalents. The analog circuit, which implements the whole process, has been synthesised, and simulation results including Monte Carlo analysis are provided, in order to verify the robustness of the proposed circuit and to compare its dynamics with prototype biological behaviour. Copyright © 2012 John Wiley & Sons, Ltd.     

A simulation study of high‐order CMOS hyperbolic‐sine filters

This paper advances the field of externally linear–internally nonlinear (ELIN) filters by introducing a synthesis method that enables the design of high‐order class‐AB sinh filters by means of complementary metal–oxide semiconductor (CMOS) weak‐inversion sinh integrators comprising only one type of devices in their translinear loops. The proposed transistor‐level synthesis approach is demonstrated through the examples of (1) a biquadratic and (2) a fifth‐order filter, and their simulated performance is studied. The biquadratic filter achieves a dynamic range of 94 dB and has a tunable quality factor Q up to the value of 8, whereas its natural frequency can be tuned for four orders of magnitude. Its static power consumption amounts to 6.2 μW for Q = 1 and f_o = 2 kHz. The fifth‐order Chebyshev sinh CMOS filter with a cut‐off frequency of 100 Hz, a pass band ripple of 1 dB, and a power consumption of ~300 nW is compared head‐to‐head with its pseudo‐differential class‐AB CMOS log domain counterpart. The sinh filter achieves similar or better signal‐to‐noise ratio (SNR) and signal‐to‐noise‐plus‐distortion ratio (SNDR) performances with half the capacitor area but at the expense of higher power consumption from the same power supply level. All three presented filter topologies are novel. Cadence design framework simulations have been performed using the commercially available 0.35 µm AMS (austriamicrosystems) process parameters. Copyright © 2013 John Wiley & Sons, Ltd.     

A higher-order unsplit-field perfectly matched layer for the reflectionless truncation of 3-D spherical FDTD lattices

An enhanced higher-order finite-difference time-domain (FDTD) method for the systematic implementation of 3-D reflectionless perfectly matched layers (PML) in spherical coordinates is presented. By establishing a topologically unsplit-field formulation, the novel technique introduces accurate nonstandard schemes that eliminate the notably intricate lattice dispersion errors. Moreover, the wider spatial increments are treated via self-adaptive compact operators, while a mesh expansion process yields a significant reduction of the absorber's depth. For the temporal variable, the proposed method employs a multistage leapfrog integration that guarantees stability and excitation universality. Hence, because of the optimal configuration of the new PML, it attains a critical annihilation of both propagating and spurious wave families, even for complicated domains. Numerical investigation verifies the superiority of the higher-order algorithm via several unbounded radiation and scattering spherical problems.     

Structure and thermoelectric properties of higher manganese silicides synthesized by pack cementation

Higher manganese silicides (HMS) are promising alternative materials for middle to high temperature thermoelectric applications as a low-cost, non-toxic and highly stable p-type leg. Many of the preparation methods that have been reported previously require long-time and energy consuming processes, as well as expensive equipment, and often do not result in a material of sufficient quality. In this study, the simple, cost-effective and eco-friendly technique of pack cementation is applied. HMS powders synthesized at different experimental conditions are studied and compared considering their structure, composition, short-term thermal stability in air and thermoelectric properties. X-ray diffraction analysis, X-ray photoelectron spectroscopy, scanning electron microscopy, thermogravimetry and thermoelectric measurements (in terms of Seebeck coefficient, electrical and thermal conductivity) were employed for the characterization of the material and evaluation of its performance. All samples were identified as HMS and only some negligible traces of MnSi were detected. They moderately oxidize when heated non-isothermally under air atmosphere up to 1473 K, while the presence of HMS remains dominant even at such high temperatures. Their thermoelectric properties were remarkable for an undoped material, with a maximum figure of merit (ZT) of 0.47 at 777 K. Pack cementation appeared to have a great potential as the synthesis route of high-efficiency HMS.