A mixed-signal RAM decision-feedback equalizer for disk drives

A mixed-signal RAM decision-feedback equalizer (DFE) that operates at 90 Mb/s is described. In the analog domain, the DFE subtracts intersymbol interference caused by the past four outputs. The equalized signal is fed into a nonuniform flash analog-to-digital converter (ADC) to produce the decision output and error signal used to adapt the RAM contents in the digital domain. With a 5 V supply voltage, the power dissipation is 260 mW during steady-state operation. The active area is 4.5 mm² in a 1 μm CMOS process     

Technique for Producing Mullite and Other Mixed-Oxide Systems

Mixed-oxide systems are of interest in a variety of technical ceramic applications. The key in many systems is to achieve a high degree of homogeneity, approaching the molecular level. A technique for producing mixed oxides via direct oxidation of mixtures of organometallic compounds is discussed as a potential route. Preliminary work performed on producing mullite is discussed.     

Neural Network Feedback Control: Work at UTA’s Automation and Robotics Research Institute

This is an outline of research in neural networks for feedback control done since the mid 1990s at the Automation and Robotics Research Institute (ARRI) of The University of Texas at Arlington (UTA). It shows how the developments of Intelligent Control Systems based on neural networks have followed three main generations. This statement provides a short, broad-brush perspective on the development of intelligent neural feedback controllers.     

CADRE: An Asynchronous Embedded DSP for Mobile Phone Applications

Asynchronous design techniques have a number of compelling features that make them suited for complex system on chip designs. However, it is necessary to develop practical and efficient design techniques to overcome the present shortage of commercial design tools. This paper describes the development of CADRE (Configurable Asynchronous DSP for Reduced Energy), a 750K transistor, high performance, low-power digital signal processor IP block intended for digital mobile phone chipsets. A short time period was available for the project, and so a methodology was developed that allowed high-level simulation of the design at the earliest possible stage within the conventional schematic entry environment and simulation tools used for later circuit-level performance and power consumption assessment. Initial modeling was based on C behavioral models of the various data and control components, with the many asynchronous control circuits required automatically generated from their specifications. This has enabled design options to be explored and unusual features of the design, such as the Register Bank which is designed to exploit data access patterns, are presented along with the power and performance results of the processor as a whole.     

Surface-acoustic-wave frequency-domain limiter

It is shown that, by exploiting the 2-dimensional structure of a SAW substrate to propagate different frequency components over distinct physical paths, the amplitude-limiting process that occurs at high power levels can be made `local? in the frequency domain. One application of such a frequency-domain limiter is to suppress CW interference in spread-spectrum communications.