Broad-band MMICs based on modified loss-compensation method using 0.35-/spl mu/m SiGe BiCMOS technology

Using the concept of loss compensation, novel broad-band monolithic microwave integrated circuits (MMICs), including an amplifier and an analog multiplier/mixer, with LC ladder matching networks in a commercial 0.35-mum SiGe BiCMOS technology are demonstrated for the first time. An HBT two-stage cascade single-stage distributed amplifier (2-CSSDA) using the modified loss-compensation technique is presented. It demonstrates a small-signal gain of better than 15 dB from dc to 28 GHz (gain-bandwidth product=157 GHz) with a low power consumption of 48 mW and a miniature chip size of 0.63 mm² including testing pads. The gain-bandwidth product of the modified loss-compensated CSSDA is improved approximately 68% compared with the conventional attenuation-compensation technique. The wide-band amplifier achieves a high gain-bandwidth product with the lowest power consumption and smallest chip size. The broad-band mixer designed using a Gilbert cell with the modified loss-compensation technique achieves a measured power conversion gain of 19 dB with a 3-dB bandwidth from 0.1 to 23 GHz, which is the highest gain-bandwidth product of operation among previously reported MMIC mixers. As an analog multiplier, the measured sensitivity is better than 3000 V/W from 0.1 to 25 GHz, and the measured low-frequency noise floor and corner frequency can be estimated to be 20 nV/sqrt(Hz) and 1.2 kHz, respectively. The mixer performance represents state-of-the-art result of the MMIC broad-band mixers using commercial silicon-based technologies     

Viable：设计折射生活体验

从上个世纪九十年代中期开始，无定型的造型在设计中占据了主导。十年之后，人们的审美和设计标准发生了变化。几何原理的广泛应用使得生活物品的设计出现了“硬边”（产品的棱线和轮廓）与“精确”之风的回潮。也许是人们渴望在这个不稳定的世界中寻求稳定的元素，也许是为了用简单直白的设计来掩饰以往设计中复杂计算的造型。总之，设计师对成熟稳重的几何形式表现得情有独钟。这种席卷而来的感觉体现了一种设计的成熟，而Viable工作室的设计就是其中的代表；不仅如此，他们的设计还反映出了每个人对生活的不同理解。[编者按]     

A new iterative order reduction (IOR) method for eigensolutions of large structures

Order reduction is a computationally efficient method to estimate some lowest eigenvalues and the corresponding eigenvectors of large structural systems by reducing the order of the original model to a smaller one. But its accuracy is limited to a small range of frequencies that depends on the selection of the retained degrees of freedom. This paper proposes a new iterative order reduction (IOR) technique to obtain accurately the eigensolutions of large structural systems. The technique retains all the inertia terms associated with the removed degrees of freedom. This hence leads to the reduced mass matrix being in an iterated form and the reduced stiffness matrix constant. From these mass and stiffness matrices, the eigensolutions of the reduced system can be obtained iteratively. On convergence the reduced system reproduces the eigensolutions of the original structure. A proof of the convergence property is also presented. Applications of the method to a practical GARTEUR structure as well as a plate have demonstrated that the proposed method is comparable to the commonly used Subspace Iteration method in terms of numerical accuracy. Moreover, it has been found that the proposed method is computationally more efficient than the Subspace Iteration method. Copyright © 2003 John Wiley & Sons, Ltd.     

Silicon-to-steel bonding using rapid thermal annealing

This paper presents the rapid, low-temperature bonding between silicon and steel using the rapid thermal annealing process. Three different thin-film adhesion layer systems including silver, gold, and nickel were utilized as the intermediate bonding material to assist the eutectic Pb/Sn bonding between silicon and steel. The bonding temperature was set at 220/spl deg/C for 20 s, with a 20-s ramp-up time. Five experiments were conducted to determine the strength of the bond, including static tensile and compressive four-point bend tests, axial extension tests, tensile bending fatigue tests, and corrosion resistance tests. The test results have shown that the gold adhesion layer is the most robust, demonstrating minimal creep during fatigue tests, no delamination during the tensile or compressive four-point bend tests, and acceptable strength during the axial extension tests. Additionally, all adhesion layers have withstood four months of submersion in various high-temperature solutions and lubricants without failure. Simulations of the axial stresses and strains that developed during the four-point bend and axial extension tests were performed and showed that the presence of the silicon die provides a local reinforcement of the bond as observed in the experimental tests.     

Enhanced light output in nitride-based light-emitting diodes by roughening the mesa sidewall

In this letter, we will report on a nitride-based light emitting diode with a mesa sidewall roughening process that increases light output power. The fabricated GaN-based light-emitting diode (LED) wafers were first treated through a photoelectrochemical (PEC) process. The Ga/sub 2/O/sub 3/ layers then formed around the GaN : Si n-type mesa sidewalls and the bottoms mesa etching regions. Selective wet oxidation occurred at the mesa sidewall between the p- and the n-type GaN interface. The light output power of the PEC treated LED was seen to increase by about 82% which was caused by a reduced index reflectance of GaN-Ga/sub 2/O/sub 3/-air layers, by a rough Ga/sub 2/O/sub 3/ surface, by a microroughening of the GaN sidewall surface, and by a selective oxidation step profile of the mesa sidewall that increases the light-extraction efficiency from the mesa sidewall direction. Consequently, this wet PEC treated process is suitable for high powered nitride-based LEDs lighting applications.     

Design Techniques of CMOS Ultra-Wide-Band Amplifiers for Multistandard Communications

This paper presents design techniques of CMOS ultra-wide-band (UWB) amplifiers for multistandard communications. The goal of this paper is to propose a compact, simple, and robust topology for UWB low-noise amplifiers, which yet consumes a relatively low power. To achieve this goal, a common-gate amplifier topology with a local feedback is employed. The first amplifier uses a simple inductive peaking technique for bandwidth extension, while the second design utilizes a two-stage approach with an added gain control feature. Both amplifiers achieve a flat bandwidth of more than 6 GHz and a gain of higher than 10 dB with supply voltages of 1.8-2.5 V. Designs with different metal thicknesses are compared. The advantage of using thick-metal inductors in UWB applications depends on the chosen topology.     

Ionothermal synthesis of a three-dimensional zinc phosphate with DFT topology using unstable deep-eutectic solvent as template-delivery agent

A three-dimensional zinc phosphate compound with DFT topology, designated as ZnPO₄-EU1, has been synthesized by an ionothermal approach from the system HF-ZnO–P₂O₅-choline chloride-imidazolidone. Ethylenediamine, derived from decomposition of the imidazolidone component of the deep-eutectic solvent (DES) itself, is delivered to the synthesis and serves as an appropriate template for ZnPO₄-EU1. Experiments in which the synthesis conditions were varied showed that ZnPO₄-EU1 may be prepared over a wide molar ratio of P/Zn = 0.55–13.0. Powder X-ray diffraction patterns have been obtained at intervals to track the crystallization process of this material. The experimental data show that Zn₃(PO₄)₂ · 4H₂O (a dense phase) was first isolated from the DES after reaction for 1 h. Subsequently, the pure phase of ZnPO₄-EU1 was obtained with increasing crystallization time from 12 h to 72 h. The experimental results show that the nucleation and crystallization take place with relatively low levels of solvent degradation, demonstrating that zinc phosphate with a three-dimensional framework can be synthesized by in situ generation of an appropriate template using an unstable DES at high temperatures (150–200 °C).     

熟悉而又陌生

《Frame》总第46期向读者展示了许多有意思的想法和创意的细节下面是从中摘选出来的设计和空间方案他们都运用到了我们身边很熟悉的元素，在这里“腐朽”一下化神奇了。[编者按]