Air bearing design, optimization, stability analysis andverification for sub-25 nm flying

Three sub-25 nm fly height sliders are presented for near contact recording. The designs are geared towards the goal of achieving 10 Gb/in ² areal density. The optimization procedure presented shows promise for facilitating achievement of this goal. The dynamic simulations show the stability of these designs when disturbed from their steady state conditions     

Measurement and modeling of the sidewall threshold voltage ofmesa-isolated SOI MOSFETs

Five-terminal silicon-on-insulator (SOI) MOSFETs have been characterized to determine the threshold voltage at the front, back, and sidewall as a function of the body bias. The threshold voltage shift with the body bias at the front and back interfaces can be explained by the standard bulk body effect equation. However, the threshold voltage shift at the sidewall is smaller than predicted by this equation and saturates at large body biases. This anomalous behavior is explained by two-dimensional charge sharing between the sidewall and the front and back interfaces. An analytical model that accounts for this charge sharing by a simple trapezoidal approximation of the depletion regions and correctly predicts the sidewall threshold voltage shift and its saturation is discussed. The model makes it possible to measure the sidewall threshold even when it is larger than the front threshold voltage     

A 4-MB on-chip L2 cache for a 90-nm 1.6-GHz 64-bit microprocessor

A 4-MB L2 data cache was implemented for a 64-bit 1.6-GHz SPARC(r) RISC microprocessor. Static sense amplifiers were used in the SRAM arrays and for global data repeaters, resulting in robust and flexible timing operation. Elimination of the global clock grid over the SRAM array saves power, enabled by combining the clock information with array select signals. Redundancy was implemented flexibly, with shift circuits outside the main data array for area efficiency. The chip integrates 315 million transistors and uses an 8-metal-layer 90-nm CMOS process.     

60m高度处单片露天超高混凝土悬臂墙的设计与施工

通过采用竖向预应力技术 ,解决了 60m高度处单片 8m高悬臂钢筋混凝土墙根部裂缝宽度超过规范限值的问题 ;采用将预应力钢绞线顶端锚固于墙高中段等结构和施工措施 ,控制墙体长细比不超过 3 0 ,减少了由于长细比过大对墙体承载力的不利影响     

高频脉冲电铸Ni-Co纳米复合块体微观结构分析

采用高频脉冲电铸工艺制备出了镍钴纳米复合块体材料，利用场发射扫描电镜、能谱和X射线衍射的方法，重点研究了复合块体沉积层的表面形貌、相结构和结晶取向。结果表明．高频率和润湿剂的添加对沉积层的细化有重要影响，高频脉冲电铸能够获得微观组织致密、均匀的复合块体材料。     

高炉炉渣流动性的实验研究

以宝钢高炉渣中的四大组元(CaO,SiO2,Al2O3,MgO)为基础,实验研究MgO,Al2O3含量及碱度对炉渣的熔化性温度和流动性的影响.结果表明,炉渣中Al2O3含量控制在16%,配制适量的MgO(9%～10%),在1 500℃以上的高温区域,炉渣仍能保持正常的流动性,适合炉缸温度充沛的高炉使用;MgO含量由6%增加到10%时,较明显地降低了炉渣粘度,粘度的递减值约为0.07～0.15 Pa.s.     

Modeling Power Supply Noise in Delay Testing

Excessive power supply noise during test can cause overkill. This article discusses two models for supply noise in delay testing and their application to test compaction. The proposed noise models avoid complicated power network analysis, making them much faster than existing power noise analysis tools. can cause performance degradation and     

UV-LIGA深度光刻机平滑衍射技术研究

UV-LIGA深度光刻技术是加工微型机电系统的一项重要的微细加工技术。介绍了一种平滑衍射效应的位错强度叠加原理，它采用了蝇眼积分透镜去平滑衍射，并模拟数值计算了硅片表面的光强分布，最后给出了光刻结果。     

Quantifying Organization by Means of Entropy

With the aim to reduce disorder and improve efficiency, nodes in an ad hoc network run a self-organization scheme to cooperatively organize the network. Although metrics such as complexity or self-stability are commonly used for evaluation, to the best of our knowledge, none of them quantifies the efficiency to build and maintain an organization (order). We henceforth apply the notion of entropy to ad hoc type wireless networks facilitating a quantification of the internal organizational state generated by different self-organization schemes. Invoking node and link failure probabilities, we expose the dependency of the organizational state on the self-organization protocol of choice.     

一种带有阀芯关闭位置电监视的二通插装阀

该文介绍了一种带有阀芯关闭位置电监视的二通插装阀，对其功能、优点和电器特性详细说明，并结合实例说明其安全应用方式。