A miniaturized silicon-based ground Ring Guarded patch resonator and filter

A new miniaturized ground ring guided microstrip patch filter developed on the silicon wafer using micromachined technology is reported. The ground shunt can be used to lower the operating frequency up to one-third as compared to the traditional patch resonator. The size of the designed band pass filter operating in 5.17 GHz is only 8.7 mm/spl times/2.9 mm.     

Modeling study of the impact of surface roughness on silicon and Germanium UTB MOSFETs

We outlined a simple model to account for the surface roughness (SR)-induced enhanced threshold voltage (V/sub TH/) shifts that were recently observed in ultrathin-body MOSFETs fabricated on <100> Si surface. The phenomena of enhanced V/sub TH/ shifts can be modeled by accounting for the fluctuation of quantization energy in the ultrathin body (UTB) MOSFETs due to SR up to a second-order approximation. Our model is then used to examine the enhanced V/sub TH/ shift phenomena in other novel surface orientations for Si and Ge and its impact on gate workfunction design. We also performed a calculation of the SR-limited hole mobility (/spl mu//sub H,SR/) of p-MOSFETs with an ultrathin Si and Ge active layer thickness, T/sub Body/<10 nm. Calculation of the electronic band structures is done within the effective mass framework via the Luttinger Kohn Hamiltonian, and the mobility is calculated using an isotropic approximation for the relaxation time calculation, while retaining the full anisotropy of the valence subband structure. For both Si and Ge, the dependence of /spl mu//sub H,SR/ on the surface orientation, channel orientation, and T/sub Body/ are explored. It was found that a <110> surface yields the highest /spl mu//sub H,SR/. The increasing quantization mass m/sub z/ for <110> surface renders its /spl mu//sub H,SR/ less susceptible with the decrease of T/sub Body/. In contrast, <100> surface exhibits smallest /spl mu//sub H,SR/ due to its smallest m/sub z/. The SR parameters, i.e. autocorrelation length (L) and root-mean-square (/spl Delta//sub rms/) used in this paper is obtained from the available experimental result of Si<100> UTB MOSFETs, by adjusting these SR parameters to obtain a theoretical fit with experimental data on SR-limited mobility and V/sub TH/ shifts. This set of SR parameters is then employed for all orientations of both Si and Ge devices.     

Equivalent circuit model of on-wafer CMOS interconnects for RFICs

This paper investigates the properties of the on-wafer interconnects built in a 0.18-/spl mu/m CMOS technology for RF applications. A scalable equivalent circuit model is developed. The model parameters are extracted directly from the on-wafer measurements and formulated into empirical expressions. The expressions are in functions of the length and the width of the interconnects. The proposed model can be easily implemented into commercial RF circuit simulators. It provides a novel solution to include the frequency-variant characteristics into a circuit simulation. The silicon-verified accuracy is proved to be up to 25 GHz with an average error less than 2%. Additionally, equivalent circuit model for longer wires can be obtained by cascading smaller subsections together. The scalability of the propose model is demonstrated.     

共面转换液晶显示器中获得对比度高于1:600的新技术

薄膜晶体管液晶电视(TFT-LCD TV)因为具有薄、轻、紧凑和可随意放置的特点，已经占据了大部分电视机市场。除了这些物理特性以外，最重要的特性是已具有了良好像质的对比度。为了将对比度提高到1：600以上，对偏振片膜、背光源板、滤色片树脂、电极锥角和摩擦条件等都进行了研究。优化的背光板组合，光滑的电极锥角和摩擦方法的控制是提高对比度的主要控制因素。应用新开发的滤色片树脂，对获得高对比度最为有效。     

Modeling and analysis of hierarchical cellular networks with general distributions of call and cell residence times

We present an analytic model for the performance evaluation of hierarchical cellular systems, which can provide multiple routes for calls through overflow from one cell layer to another. Our model allows the case where both the call time and the cell residence time are generally distributed. Based on the characterization of the call time by a hyper-Erlang distribution, the Laplace transform of channel occupancy time distribution for each call type (new call, handoff call, and overflow call) is derived as a function of the Laplace transform of cell residence time. In particular, overflow calls are modeled by using a renewal process. Performance measures are derived based on the product form solution of a loss system with capacity limitation. Numerical results show that the distribution type of call time and/or cell residence time has influence on the performance measure and that the exponential case may underestimate the system performance.     

10 Gb/s Linear Full-Rate CMOS Phase Detector for Clock Data Recovery Circuit

An improved linear full-rate CMOS 10 Gb/s phase detector is proposed. The improved phase detector overcomes the difficulties in realizing the full-rate operation by adding an I/Q splitter for the input data. Such a topology enlarges the pulse width of output signals to ease the full clock rate operation and the problem of the half period skew in the whole clock data recovery system. The proposed topology is able to provide a good linearity over a wider operating range of input phase offset compared to that of existing designs. The phase detector using the Chartered 0.18 μ m CMOS process is capable of operating up to a 10 GHz clock rate and 10 Gb/s input data for a 1.8 V supply voltage with 31 mW power consumption.     

Electrical and optical activation studies of Si-implanted GaN

Comprehensive and systematic electrical and optical activation studies of Si-implanted GaN were made as a function of ion dose and anneal temperature. Silicon ions were implanted at 200 keV with doses ranging from 1×10¹³ cm^?2 to 5×10¹⁵ cm^?2 at room temperature. The samples were proximity-cap annealed from 1050°C to 1350°C with a 500-Å-thick AlN cap in a nitrogen environment. The optimum anneal temperature for high dose implanted samples is approximately 1350°C, exhibiting nearly 100% electrical activation efficiency. For low dose (≤5×10¹⁴ cm^?2) samples, the electrical activation efficiencies continue to increase with an anneal temperature through 1350°C. Consistent with the electrical results, the photoluminescence (PL) measurements show excellent implantation damage recovery after annealing the samples at 1350°C for 20 sec, exhibiting a sharp neutral-donor-bound exciton peak along with a sharp donor-acceptor pair peak. The mobilities increase with anneal temperature, and the highest mobility obtained is 250 cm²/Vs. The results also indicate that the AlN cap protected the implanted GaN layer during high-temperature annealing without creating significant anneal-induced damage.     

High‐Strength,Durable All‐Silk Fibroin Hydrogels with Versatile Processability toward Multifunctional Applications

Hydrogels are the focus of extensive research due to their potential use in fields including biomedical, pharmaceutical, biosensors, and cosmetics. However, the general weak mechanical properties of hydrogels limit their utility. Here, pristine silk fibroin (SF) hydrogels with excellent mechanical properties are generated via a binary‐solvent‐induced conformation transition (BSICT) strategy. In this method, the conformational transition of SF is regulated by moderate binary solvent diffusion and SF/solvent interactions. β‐sheet formation serves as the physical crosslinks that connect disparate protein chains to form continuous 3D hydrogel networks, avoiding complex chemical and/or physical treatments. The Young's modulus of these new BSICT–SF hydrogels can reach up to 6.5 ± 0.2 MPa, tens to hundreds of times higher than that of conventional hydrogels (0.01–0.1 MPa). These new materials fill the “empty soft materials' space” in the elastic modulus/strain Ashby plot. More remarkably, the BSICT–SF hydrogels can be processed into different constructions through different polymer and/or metal‐based processing techniques, such as molding, laser cutting, and machining. Thus, these new hydrogel systems exhibit potential utility in many biomedical and engineering fields.     

Three-dimensional interconnect for multilayer module packages with selectively anodised aluminium substrate

It is reported that 3-D interconnects fabricated with a selectively anodised aluminium process for a multilayer module package can be used to evaluate high-frequency performance. The proposed method of fabricating vertical interconnects is easier and more cost-effective than other RF MEMS processes. To transfer RF signals vertically, coaxial hermetic seal vias with characteristic 50 Omega impedances and embedded anodised aluminium vias with a solder ball attachment and flip-chip bonding were used. The optimised interconnect structure demonstrated RF characteristics with an insertion loss of less than 1.55 OmegadB and a return loss of less than 12.25 OmegadB over a broad bandwidth ranging from 0.1 to 10 OmegaGHz. Experimental results suggest that the developed technology, which is based on selectively anodised aluminium, can be applied to new 3-D packaging solutions.