Can multiple subchannels improve the delay performance of RTS/CTS-based MAC schemes?

We analyze the delay performance of RTS/CTS-based (Request-To-Send/Clear-To-Send) multi-channel MAC (Medium Access Control) schemes for wireless networks. These schemes usually employ multiple data subchannels for data transmission and one control subchannel to send the RTS/CTS dialogue for channel reservation. Through theoretical analysis and simulations, we show that, in fully-connected networks, such multi-channel MAC schemes suffer longer delays than the corresponding single channel MAC scheme, that puts the RTS/CTS dialogue on the same channel as data packet transmissions. This conclusion holds even when data packets have different priorities and higher priority traffic is sent ahead of lower priority traffic.     

Adaptively Grouped Multilevel Space-Time Trellis Codes

Grouped multilevel space-time trellis codes (GMLSTTCs) utilize multilevel coding (MLC), antenna grouping and space time trellis codes (STTCs) for simultaneously providing coding gain, diversity improvement and increased spectral efficiency. The performance of GMLSTTCs is limited due to predefining of the antenna groups. It has been shown that when perfect or partial channel state information is available at the transmitter, the performance and capacity of space-time coded system can be further improved. In this paper, we present a new code designed by combining MLC, STTCs, antenna grouping and channel state information at transmitter, henceforth referred to as adaptively grouped multilevel space time trellis codes (AGMLSTTCs). AGMLSTTCs use a single full-diversity STTC at initial some levels and multiple STTCs at some later levels. The single full diversity STTC at each initial level spans all transmit antennas and the STTC at each later level spans a group of transmit antennas. The channel state information at the transmitter is used to adaptively group the transmit antennas for the later levels. Instantaneous channel power gain is calculated between each transmit antenna and all the receive antennas. A subset of transmit antennas having maximum channel power gain is selected to form a group. The simulation results show that AGMLSTTCs enable to transmit more than one data symbol per time slot with improved error performance over GMLSTTCs with predefined transmit antenna grouping.     

A 100-MHz macropipelined VAX microprocessor

A macropipelined CISC microprocessor was implemented in a 0.75-μm CMOS 3.3-V technology. The 1.3-million-transistor custom chip measures 1.62×1.46 cm² and dissipates 16.3 W. The 100-MHz parts were benchmarked at 50 SPEC marks. The on-chip clocking system and several high-performance logic and circuit techniques are described. Macroinstruction handling, micropipeline management, and control store structures highlight the design architecture. The hierarchical array organization and fast tag comparison technique of the primary cache are discussed. Power estimation procedures are outlined, and the results are compared to measurements. Physical design and verification methods, and CAD tools are also described. After extensive functional verification efforts are described, chip and system test results are presented     

Interference suppression by biased nonlinearities

It is shown that, when the input signal-to-interference ratio (SIR) is small, a biased nonlinearity that has a dead zone below some threshold value can provide a large enhancement in output SIR and signal-to-interference-plus-intermodulation ratio (SIIMR) if the threshold is set equal or close to the amplitude of the strong interference. In the absence of noise, the output SIR and SIIMIR are virtually independent of the input SIR, however low the latter may be. It Is shown that, for a dead-zone limiter, the output SIIMR in this case is -4.93 dB regardless of the input SIR. Under strong interference, any noise present in the input reduces the SIR and SIIMR improvement, but a biased nonlinearity can still provide an output SIR and SIIMR superior to the input SIR, i.e. an output SIIMR 6.35 dB below the input signal-to-noise ratio (SNR) instead of 6.02 dB below the input SIR as is the case with hard limiting     

Indium Gallium Arsenide Quantum Dot Gate Field-Effect Transistor Using II–VI Tunnel Insulators Showing Three-State Behavior

This paper presents an indium gallium arsenide (InGaAs) quantum dot gate field-effect transistor (QDG-FET) that exhibits an intermediate “i” state in addition to the conventional ON and OFF states. The QDG-FET utilized a II–VI gate insulator stack consisting of lattice-matched ZnSe/ZnS/ZnMgS/ZnS/ZnSe for its high-κ and wide-bandgap properties. Germanium oxide (GeO _x )-cladded germanium quantum dots were self-assembled over the gate insulator stack, and they allow for the three-state behavior of the device. Electrical characteristics of the fabricated device are also presented.     

Analysis of a Disc-Loaded Circular Waveguide for Interaction Impedance of a Gyrotron Amplifier

A rigorous electromagnetic analysis of a circular waveguide loaded with axially periodic annular discs was developed in the fast-wave regime, considering finite axial disc thickness and taking into account the effect of higher order space harmonics in the disc-free region and higher order modal harmonics in the disc-occupied region of the structure. The quality of the disc-loaded circular waveguide was evaluated with respect to its azimuthal interaction impedance that has relevance to the gain of a gyrotron millimeter-wave amplifier (gyro-traveling-wave tube) in which such a loaded waveguide finds application as a wideband interaction structure. The results of electromagnetic analysis of the structure with respect to both the dispersion and azimuthal interaction impedance characteristics were validated against the commercially available code: high frequency structure simulator (HFSS). The analysis predicts that the value of the interaction impedance at a given frequency decreases with the increase of the disc hole radius and disc periodicity. The change of the axial disc thickness does not significantly change the value of the interaction impedance though it shifts the frequency range over which appreciable interaction impedance is obtained. Out of the three disc parameters, namely the disc hole radius, thickness and periodicity, the lattermost is most effective in controlling the value of the azimuthal interaction impedance. However, the passband of frequencies and the center frequency of the passband both decrease with the increase of the disc periodicity. Moreover, the disc periodicity that provides large azimuthal interaction impedance would in general be different from that giving the desired dispersion shape for wideband interaction in a gyro-TWT, suggesting a trade-off in the value of the disc periodicity to be chosen.     

Novel Quantum Dot Gate FETs and Nonvolatile Memories Using Lattice-Matched II–VI Gate Insulators

This paper presents the successful use of ZnS/ZnMgS and other II–VI layers (lattice-matched or pseudomorphic) as high-k gate dielectrics in the fabrication of quantum dot (QD) gate Si field-effect transistors (FETs) and nonvolatile memory structures. Quantum dot gate FETs and nonvolatile memories have been fabricated in two basic configurations: (1) monodispersed cladded Ge nanocrystals (e.g., GeO _x -cladded-Ge quantum dots) site-specifically self-assembled over the lattice-matched ZnMgS gate insulator in the channel region, and (2) ZnTe-ZnMgTe quantum dots formed by self-organization, using metalorganic chemical vapor-phase deposition (MOCVD), on ZnS-ZnMgS gate insulator layers grown epitaxially on Si substrates. Self-assembled GeO _x -cladded Ge QD gate FETs, exhibiting three-state behavior, are also described. Preliminary results on InGaAs-on-InP FETs, using ZnMgSeTe/ZnSe gate insulator layers, are presented.     

Optical backbone and control of attocell network

Photonic Network Communications - For serving futuristic applications like distributed robotic systems with robots equipped with humanoid intelligence, wireless access to high-performance computing...     

A source degenerated LC quadrature VCO (SD-QVCO) using 0.18-μm SiGe BiCMOS

This letter presents a fully integrated BiCMOS quadrature voltage-controlled oscillator (QVCO). The QVCO consists of two nMOSFET cross-coupled oscillator stacked in series with source degenerated HBT transistors. SiGe HBT introduces low flicker noise compared to CMOS devices. To generate quadrature phase signals with strong coupling strength, the proposed design uses two MOS-coupled LC-tank cores instead of passive device-coupled cores. This source degeneration topology can improve the phase noise performance of the QVCO as compared to the sub-VCO. The proposed QVCO has been implemented with the TSMC 0.18 μm SiGe 3P6M BiCMOS process, can generate quadrature signals in the frequency range of 4.52–5.05 GHz with core power consumption of 5.76 mW at the dc bias of 1.8 V. At 4.53 GHz, phase noise at 1 MHz offset is ?124.52 dBc/Hz. The die area of the fabricated prototype is 0.453 × 0.898 mm².     

A single-stage zero-voltage zero-current-switched full-bridge DCpower supply with extended load power range

A single-stage power-factor-corrected pulsewidth modulation power converter with extended load power range is presented. The topology is based on a zero-voltage zero-current-switched full-bridge (ZVZCS-FB) inverter. Steady-state analysis of the topology shows that by operating the LC load filter in discontinuous mode, the DC-link voltage remains bounded and independent of the load level. Therefore, the load power range can be further expanded, including the no-load operating condition. The analysis also shows that the extension of the load power range is achieved without any penalty in: (1) the input power factor (due to the input current waveshaping feature); (2) the power converter efficiency (due to ZVZCS and the single-stage features); and (3) the load voltage quality (due to the high bandwidth of the phase control loop). Simulated and experimental results are included to show the feasibility of the proposed scheme