Sub-1 V band-gap based and MOS threshold-voltage based voltage references in 0.13 µm CMOS

Portable and implantable device applications require low supply voltage reference circuits due to increasing trend for lower power requirements. Voltage references have been proposed for operation below 1 V for CMOS and a comprehensive analysis of the behavior of the different topologies is needed for ultra-low power designs, in order to select the right circuit topology for a given requirement. This work compares two major classes of voltage reference topologies: threshold voltage (V_T0)-based and (V_G0) bandgap voltage-based reference circuits. Four different topologies of voltage-reference designs with 1-V supply were designed and fabricated in 130 nm CMOS process. Monte Carlo analysis shows the variability of the references and of their temperature coefficients (TC), and the results are compared to measured samples. Simulations and measurements show that the threshold voltage-based references are more susceptible to the variations in the CMOS fabrication process.     

Analysis of high voltage step-up nonisolated DC–DC boost converters

A high voltage step-up nonisolated DC–DC converter based on coupled inductors suitable to photovoltaic (PV) systems applications is proposed in this paper. Considering that numerous approaches exist to extend the voltage conversion ratio of DC–DC converters that do not use transformers, a detailed comparison is also presented among the proposed converter and other popular topologies such as the conventional boost converter and the quadratic boost converter. The qualitative analysis of the coupled-inductor-based topology is developed so that a design procedure can be obtained, from which an experimental prototype is implemented to validate the theoretical assumptions.     

Finding Multiple Equivalence-Preserving Transformations in Combinational Circuits through Incremental-SAT

This paper introduces an approach to effectively exploit incremental SAT in order to search for multiple equivalence-preserving transformations of combinational circuits. Typical applications, such as redundancy removal with observability and external care conditions, adequate abstractions and other optimizations used in a state-of-the-art SAT-based model checker, can reap benefits from the proposed strategies. Our techniques exploit SAT incrementality, by iteratively refining the set of candidate transformations with a counter-example driven analysis, until an unsatisfiable point is reached. The key point of our technique is the ability to address satisfiable instances first, where SAT solvers are generally much faster than with unsatisfiable runs. We also discuss partitioning and problem reduction issues, that are fundamental in order to provide a scalable approach. Experimental results show the effectiveness of the proposed strategies.     

Sagnac loop in ring resonators for tunable optical filters

General filter architecture using co- and counterpropagation signals are studied. A specific configuration based on a Sagnac loop within a ring resonator is analyzed. Novel tuning, apart from conventional tuning, is achieved by changing the coupling ratio of a coupler through the adjustment of the equivalent loop length. Full equations describing the filter behavior in passive and active configurations, and simple closed-form formulas to compute the tuning, tolerance, and full-width at half-maximum are reported. The performance of these devices is discussed for their application as selective or channel-dropping ultra-narrow-band filters. The effect of losses and their dispersion properties are also discussed. These devices can be conveniently implemented, using silicon- or InP-integrated optic technology, for they have high free spectral ranges.     

A Time-Domain Digital-Intensive Built-In Tester for Analog Circuits

To solve test challenges in nanometer CMOS technologies, a time-domain digital-intensive built-in tester for analog circuits is proposed. The compact tester allows characterizations of AC response and DC gain for various analog circuits which have a low-pass frequency characteristic. By applying ramp signals to stimulate the circuit under test and measuring slopes and time delays of its responses, the testing can be simple and robust over process-voltage-temperature variations. Also, it is well suited for nanometer technologies because of its digital-intensive implementation. The tester was fabricated in 65 nm standard CMOS process and occupies 0.026 mm².     

Mining statistically significant associations for exploratory analysis of human sleep data.

We introduce a specialized association rule mining technique that can extract patterns from complex sleep data comprising polysomnographic recordings, clinical summaries, and sleep questionnaire responses. The rules mined can describe associations among temporally annotated events and questionnaire or summary data; e.g., the likelihood that an occurrence of a rapid eye movement (REM) sleep stage during the second 100 sleep epochs of the night is associated with moderate caffeine intake. We use chi2 analysis to ensure statistical significance of the mined rules at the level P < 0.05. Our results, obtained by mining sleep-related data from 242 human subjects, reveal clinically interesting associations among the polysomnographic and summary variables. Our experience suggests that association mining may also be useful for selection of variables prior to using logistic regression.     

An Extensible Code for Correcting Multiple Cell Upset in Memory Arrays

As the microelectronics technology continuously advances to deep submicron scales, the occurrence of Multiple Cell Upset (MCU) induced by radiation in memory devices becomes more likely to happen. The implementation of a robust Error Correction Code (ECC) is a suitable solution. However, the more complex an ECC, the more delay, area usage and energy consumption. An ECC with an appropriate balance between error coverage and computational cost is essential for applications where fault tolerance is heavily needed, and the energy resources are scarce. This paper describes the conception, implementation, and evaluation of Column-Line-Code (CLC), a novel algorithm for the detection and correction of MCU in memory devices, which combines extended Hamming code and parity bits. Besides, this paper evaluates the variation of the 2D CLC schemes and proposes an additional operation to correct more MCU patterns called extended mode. We compared the implementation cost, reliability level, detection/correction rate and the mean time to failure among the CLC versions and other correction codes, proving the CLCs have high MCU correction efficacy with reduced area, power and delay costs.     

Interoperability in semantic Web of Things: Design issues and solutions

The significant improvement in processing power, communication, energy consumption, and the size of computational devices has led to the emergence of the Internet of Things (IoT). IoT projects raise many challenges, such as the interoperability between IoT applications because of the high number of sensors, actuators, services, protocols, and data associated with these systems. Semantics solves this problem by using annotations that define the role of each IoT element and reduces the ambiguity of information exchanged between the devices. This work presents SWoTPAD, a semantic framework that helps in the development of IoT projects. The framework is designer oriented and provides a semantic language that is more user‐friendly than OWL‐S and WSML and allows the IoT designer to specify devices, services, environment, and requests. Following this, it makes use of these specifications and maps them for RESTful services. Additionally, it generates an automatic service composition engine that is able to combine services needed to handle complex user requests. We validated this approach with two case studies. The former concerns a residential security system and the latter, the cloud application deployment. The average time required for service discovery and automatic service composition corresponds to 72.9% of the service execution time in the case study 1 and 64.4% in the case study 2.     

Self‐Assembled Conjugated Thiophene‐Based Rotaxane Architectures: Structural,Computational, and Spectroscopic Insights into Molecular Aggregation

A comparative study of the self‐assembly at a variety of surfaces of a dithiophene rotaxane 1 ?β‐CD and its corresponding dumbbell, 1, by means of atomic force microscopy (AFM) imaging and scanning tunneling microscopy (STM) imaging on the micrometer and nanometer scale, respectively. The dumbbell is found to have a greater propensity to form ordered supramolecular assemblies, as a result of π–π interactions between dithiophenes belonging to adjacent molecules, which are hindered in the rotaxane. The fine molecular structure determined by STM was compared to that obtained by molecular modelling. The optical properties of both rotaxane and dumbbell in the solid state were investigated by steady‐state and time‐resolved photoluminescence (PL) experiments on spin‐cast films and diluted solutions. The comparison between the optical features of the threaded and unthreaded systems reveals an effective role of encapsulation in reducing aggregation and exciton migration for the rotaxanes with respect to the dumbbells, thus leading to higher PL quantum efficiency and preserved single‐molecule photophysics for longer times after excitation in the threaded oligomers.