基于可变S盒的分组密码算法及其在媒体网关中的应用

分组密码算法是信息安全领域中最为重要的加解密技术之一。与传统的分组密码不同，该算法具有可变的S盒和变化的循环加密结构，从而大大提高了抗差分攻击和线性攻击的能力。结合某媒体网关的设计项目，研究了该算法并详细探导了其设计方法。员后，测试了算法的实际性能。     

高功率微波可变衰减器

介绍了高功率微波可变衰减器的设计和测量结果.刀形衰减器的衰减片由通水的聚四氟乙烯制成,利用槽波导技术和截止波导技术,降低了衰减器的漏能。衰减量的变化范围是0-10dB。在工作频段内除少数测量点之外，驻波比小于1.1，可以安全使用。     

基于ADSP的分段脉冲压缩应用

论述了基于群时延的分段脉冲压缩机理，并简要介绍了ADSP2106x系列的特征，以及在基于ADSP21062的应用中分段脉压的工程实现方法和仿真结果。     

双酚A双肉桂酸酯光控取向膜

利用双酚A双肉桂酸酯光敏单体在线偏振紫外光作用下发生光交联反应,制备了光控取向膜。制备过程更为简单,不需要高温热处理过程。液晶分子的排列方向与入射紫外光偏振方向垂直。通过紫外光谱和红外光谱分析了光化学反应过程,链聚合反应与异构反应相比,链状聚合反应对于液晶的排列起重要作用。利用偏振红外光谱对取向膜的有序度值计算发现,有序值较小。利用Cano盒测试了方位锚定能的大小为1.28×10-6J/m2。取向膜的热稳定性可以达到90℃。     

增强的无线局域网安全技术分析

文章介绍了无线局域网安全技术的现状，对IEEE802．11i草案中有关认证、密钥管理、加密等方面的增强的无线局域网安全技求进行了分析。提出了基于IPsec(IP安全)的VPN安全解决方案。     

一种支持QoS片上网络路由器的设计与实现

设计了一种8端口的NoC路由器.采用简化的VOQ结构,使用双交叉开关,可连接4个IP核,开关调度具有动态、确定和公平的特点,能够提供QoS保证,并有效降低了报文排头阻塞和片上网络面积.Synopsys Design Compiler的综合结果表明,基于0.13μm工艺实现后,面积为0.62mm2,工作频率可达500MHz.     

浸灰助剂的功能及作用原理

阐述了浸灰过程中皮发生的变化及其对革性能的影响,对浸灰助剂的分类、功能和作用原理进行了分析、对浸灰助剂的研究、开发和应用提出了一些建议。     

高压电场加速食品解冻的探讨

在综述常用解冻法优缺点的基础上,提出了高压静电场解冻,介绍了这种技术的国内外发展现状,并从水的角度初步探讨了解冻机理。     

Radiation of millimeter waves from NRD leaky wave antennas withtapered transition and tuning aperture

The radiation of millimeter waves from the nonradiative dielectric (NRD) leaky wave antennas with the tapered transition and the tuning aperture is investigated. An accurate theory for the leakage constant and the phase constant of the antennas is presented, which is based on the generalized scattering parameters considering the higher-order mode interactions at the discontinuities. The associated transverse equivalent network involves the characterization of the mode couplings at two air-to-dielectric interfaces, the coupled mode analysis of the tapered transition, and the calculation of the radiation fields at the tuning aperture via the extended spectral domain approach. The interesting behavior of the present modified configuration of NRD leaky wave antennas is illustrated by typical examples. The validity of the theory is confirmed by the comparison of the theoretical results with experimental data for the limiting cases     

Optimization of test parallelism with limited hardware overhead

The main considerations for built-in self-test (BIST) for complex circuits are fault coverage, test time, and hardware overhead. In the BIST technique, exhaustive or pseudo-exhaustive testing is used to test the combinational logic in a register sandwich. If register sandwiches can be identified in a complex digitial system, it is possible to test several of them in parallel using the built-in logic block observation (BILBO) technique. Concurrent built-in logic block observation (CBILBO) technique can further improve the test time, but it requires significant hardware overhead. A systematic scheduling technique is suggested to optimize parallel tests of register sandwiches. Techniques are proposed to deal with shared registers for parallel testing. The proposed method attempts to reduce further the test time while only modestly increasing the hardware overhead.