Changes in the characteristics of CuInGaSe2 solar cells under light irradiation and during recovery: degradation analysis by the feeble light measuring method

Changes in the characteristics of CuInGaSe₂ solar cells in response to light irradiation were investigated. Then these changes, which suggest long-term degradation, were clarified using the measurement technique by feeble light. The thin-film cell of this type is considered to be “ever stable”. A stable result over the short term was also obtained in the light accelerated test of 2-SUN performed in this experiment. On the other hand, it was found that the characteristics measured with feeble light show a remarkable change over time. As a result of measuring at 0.065–105 mW/cm² light intensity, the change rate of cell output power was so intense the measurement light was weak. This finding reflects the increase in an internal defect and suggests a possibility that light irradiation exerts the influence on long-term cell performance. Moreover, by measuring with feeble light, we found that the changed output recovers by reverse voltage application. The phenomenon of recovery up on comparatively low reverse voltage can be considered as an application for maintaining stability.     

A low-impedance open-bitline array for multigigabit DRAM

The noise-generating mechanisms inherent in the open-bitline DRAM array using the 6F² (F: feature size) memory cells and techniques for reducing the noise are described. The sources of differential noise coupled to the paired bitlines laid out in two arrays are the p-well, cell plate, and the group of nonselected wordlines. It was found, by simulation and by experiment with a 0.13-μm 256-Mb test chip, that the level of noise is dramatically reduced by using a low-impedance array with careful layout featuring low-resistivity materials, tight bridging between pairs of adjacent arrays, and a small array, achieving a comparable level of noise to that seen in the twisted and folded-bitline array. On basis of these results, it turns out that the open-bitline array has a strong chance of revival in the multigigabit generation, as long as these noise reduction techniques are applied     

An 8.1-ns Column-Access 1.6-Gb/s/pin DDR3 SDRAM With an 8:4 Multiplexed Data-Transfer Scheme

Three circuit techniques for an 8.1-ns column-access 1.6-Gb/s/pin 512-Mb DDR3 SDRAM using 90-nm dual-gate CMOS technology were developed. First, an 8:4 multiplexed data-transfer scheme, which operates in a quasi-4-bit prefetch mode, achieves a 3.17-ns reduction in column-access time, i.e., from 11.3 to 8.13 ns. Second, a dual-clock latency counter reduces standby power by 22% and cycle time from 1.7 to 1.2 ns. Third, a multiple-ODT-merged output buffer enables selection of five effective-resistance values Rtt (20, 30, 40, 60, and 120 Omega) without increasing I/O capacitance. Based on these techniques, 1.6-Gb/s/pin operation with a 1.36-V power supply and a column latency of 7 was accomplished     

Thiamine pyrophosphatase activity in the Golgi apparatus of calcitonin-treated osteoclasts.

The thiamine pyrophosphatase (TPPase) activity described by Novikoff and Goldfisher was examined in osteoclasts affected by calcitonin in order to elucidate whether the morphological and functional changes of the osteoclasts have an influence over the secretion function of their Golgi apparatus. The Golgi apparatus of osteoclasts of which the ruffled border had disappeared and bone resorption discontinued as the result of treatment with calcitonin showed a slight TPPase activity. The reaction products of the enzyme in these inactive osteoclasts were distinctly fewer than that of control osteoclasts, which were not affected by calcitonin. From these results, it is suggested that there may be a connection between the morphological and functional changes of osteoclasts and the secretion function of the Golgi apparatus.     

Transport-Coefficient Dependence of Current-Induced Cooling Effect in a Two-Dimensional Electron Gas

The dependence of the current-induced cooling effect on the electron mobility??? _e is explored for a two-dimensional electron gas (2DEG) subjected to a perpendicular magnetic field. We calculate the distributions of the electrochemical potentials and the temperatures under a magnetic field, fully taking account of thermoelectric and thermomagnetic phenomena. Whereas the electrochemical potential and the electric current remain qualitatively unchanged, the temperature distribution exhibits drastic mobility dependence. The lower-mobility system has cold and hot areas at opposite corners, which results from the heat current brought about by the Ettingshausen effect in the vicinity of the adiabatic boundaries. The cooling effect is intensified by an increase in??? _e. Intriguingly, the cold and hot areas change places with each other as the mobility??? _e is further increased. This is because the heating current on the adiabatic edges due to the Righi?CLeduc effect exceeds that due to the Ettingshausen effect in the opposite direction.     

Compact solid-State switched pulsed power and its applications

Power semiconductor devices, such as insulated-gate bipolar transistors, metal-oxide-semiconductor field-effect transistors, and static-induction thyristors, are used in different kinds of pulsed power generators developed for different applications. In addition, the semiconductor opening switch is found to have very effective applications in pulsed power generation by inductive energy storage. Semiconductor switches have greatly extended the scales of pulsed power parameters, especially in repetition rate and lifetime. They have also enabled new areas of pulsed power applications, such as accelerators, flue-gas treatment, and gas lasers.     

Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester

Numerous solutions have been proposed to reduce test data volume and test application time during manufacturing testing of digital devices. However, time to market challenge also requires a very efficient debug phase. Error identification in the test responses can become impractically slow in the debug phase due to large debug data, slow tester speed, and limited memory of the tester. In this paper, we investigate the problems and solutions related to using a relatively slow and limited memory tester to observe the at-speed behavior of fast circuits. Our method can identify all errors in at-speed scan BIST environment without any aliasing and using only little extra overhead by way of a multiplexer and masking circuit for diagnosis. Our solution takes into account the relatively slower speed of the tester and the reload time of the expected data to the tester memory due to limited tester memory while reducing the test/debug cost. Experimental results show that the test application time by our method can be reduced by a factor of 10 with very little hardware overhead to achieve such advantage.     

A 1.25-inch 60-frames/s 8.3-M-pixel digital-output CMOS image sensor

The ultrahigh-definition television (UDTV) camera system requires an image sensor having four times higher resolution and two times higher frame rate than the conventional HDTV systems. Also, an image sensor with a small optical format and low power consumption is required for practical UDTV camera systems. To respond to these requirements, we have developed an 8.3-M-pixel digital-output CMOS active pixel sensor (APS) for the UDTV application. It features an optical format of 1.25inch, low power consumption of less than 600 mW at dark, while reproducing a low-noise, 60-frames/s progressive scan image. The image sensor is equipped with 1920 on-chip 10-bit analog-to-digital converters and outputs digital data stream through 16 parallel output ports. Design considerations to reproduce a low-noise, high-resolution image at high frame rate of 60 fps are described. Implementation and experimental results of the 8.3-M-pixel CMOS APS are presented.     

Polarization-, Wavelength-, and Filter-Free All-Optical Clock Recovery in a Passively Mode-Locked Laser Diode With Orthogonally Pumped Polarization-Diversity Configuration

We proposed and demonstrated all-optical clock recovery system using a monolithic mode-locked laser diode (MLLD) that operated with less sensitivity to the polarization and the wavelength of the input data signals also with no bandpass filter to eliminate the input signal-components. The keys to this new technique are the MLLD integrated with a tensile-strained quantum-well saturable absorber and a new polarization-diversity setup by signal input orthogonally polarized to the lasing polarization of the MLLD. This approach was experimentally validated in the 40 Gbps clock recovery experiments. The results exhibited excellent performance of the clock recovery with low timing jitters (<0.3 ps) remaining small dependence on the wavelength and the polarization of the input data signals and input-signal suppression less than -30 dB with no use of the bandpass filter. We also succeeded in the stable clock recovery for the input of polarization-scrambled data signals.     

1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer

This paper describes three circuit techniques for a DDR1/DDR2-compatible chip architecture designed for both high-speed and high-density DRAMs: 1) a dual-clock input-latch scheme, which reduces the excessive timing margin for random input commands by using a pair of latch circuits controlled by dual-phase one-shot clock signals, achieves a 0.9-ns reduction in cycle time from 3.05 to 2.15 ns; 2) a hybrid multi-oxide output buffer reduces the area penalty of the output buffer caused by compatible chip design from 1.35% to 0.3%; and 3) a quasi-shielded distributed data transfer scheme enables a 2.6-ns reduction in access time to 10.25 ns in both 2-b and 4-b prefetch operations. By using these techniques, we developed a 175.3-mm/sup 2/ 1-Gb SDRAM that operates as an 800-Mb/s/pin DDR2 or 400-Mb/s/pin DDR1.