Evaluation and optimization of package processing and design through solder joint profile prediction

Solder joints are generated using a variety of methods to provide both mechanical and electrical connection for applications such as flip-chip, wafer level packaging, fine pitch, ball-grid array, and chip scale packages. Solder joint shape prediction has been incorporated as a key tool to aid in process development, wafer level and package level design and development, assembly, and reliability enhancement. This work demonstrates the application of an analytical model and the Surface Evolver software in analyzing a variety of solder processing methods and package types. Bump and joint shape prediction was conducted for the design of wafer level bumping, flip-chip assembly, and wafer level packaging. The results from the prediction methodologies are validated with experimentally measured geometries at each level of design.     

Training and optimization of an artificial neural network controlling a hybrid power filter

A hybrid power compensator (HPC) consisting of a static VAr compensator and a dynamic compensator needs to be optimally controlled during the compensation of nonlinear loads. The HPC must be controlled to meet minimum requirements in terms of power factor and harmonic distortion, while at the same time minimizing its total cost. An artificial neural network (ANN) is used to control the HPC amidst a very dynamic power system environment. The performance of a reference ANN is evaluated while controlling an HPC connected to a typical nonlinear industrial load. The training and performance of the ANN is then optimized in terms of training set size, training set packing and ANN topology and the performance compared to the reference ANN. This paper highlights the importance of optimising the mentioned ANN parameters to achieve optimum ANN training and modeling accuracy. The results obtained reveals that the application of an ANN in controlling an HPC is feasible given that the ANN parameters are chosen appropriately.     

Synthesis of ZSM‐5 Films and Monoliths with Bimodal Micro/Mesoscopic Structures

A route to synthesize ZSM‐5 crystals with a bimodal micro/mesoscopic pore system has been developed in this study; the successful incorporation of the mesopores within the ZSM‐5 structure was performed using tetrapropylammonium hydroxide (TPAOH)‐impregnated mesoporous materials containing carbon nanotubes in the pores, which were encapsulated in the ZSM‐5 crystals during a solid rearrangement process within the framework. Such mesoporous ZSM‐5 zeolites can be readily obtained as powders, thin films, or monoliths.     

The First Template‐Free Growth of Crystalline Silicon Microtubes

A simple template‐free high‐temperature evaporation method was developed for the growth of crystalline Si microtubes for the first time. As‐grown Si microtubes were characterized using X‐ray diffraction, scanning electron microscopy, transmission electron microscopy, and room‐temperature photoluminescence. The lengths of the Si tubes can reach several hundreds of micrometers; some of them have lengths on the order of millimeters. Each tube has a uniform outer diameter along its entire length, and the typical outer diameter is ≈ 2–3 μm. Most of the tubes have a wall thickness of ≈ 400–500 nm, though a considerable number of them exhibit a very thin wall thickness of ≈ 50 nm. Room‐temperature photoluminescence measurement shows the as‐synthesized Si microtubes have two strong emission peaks centered at ≈ 589 nm and ≈ 617 nm and a weak emission peak centered at ≈ 455 nm. A possible mechanism for the formation of these Si tubes is proposed. We believe that the present discovery of the crystalline Si microtubes will promote further experimental studies on their physical properties and smart applications.     

Influence of device engineering on the analog and RF performances of SOI MOSFETs

This work presents a systematic comparative study of the influence of various process options on the analog and RF properties of fully depleted (FD) silicon-on-insulator (SOI), partially depleted (PD) SOI, and bulk MOSFET's with gate lengths down to 0.08 /spl mu/m. We introduce the transconductance-over-drain current ratio and Early voltage as key figures of merits for the analog MOS performance and the gain and the transition and maximum frequencies for RF performances and link them to device engineering. Specifically, we investigate the effects of HALO implantation in FD, PD, and bulk devices, of film thickness in FD, of substrate doping in SOI, and of nonstandard channel engineering (i.e., asymmetric Graded-channel MOSFETs and gate-body contacted DTMOS).     

Static energy reduction techniques for microprocessor caches

Microprocessor performance has been improved by increasing the capacity of on-chip caches. However, the performance gain comes at the price of static energy consumption due to subthreshold leakage current in cache memory arrays. This paper compares three techniques for reducing static energy consumption in on-chip level-1 and level-2 caches. One technique employs low-leakage transistors in the memory cell. Another technique, power supply switching, can be used to turn off memory cells and discard their contents. A third alternative is dynamic threshold modulation, which places memory cells in a standby state that preserves cell contents. In our experiments, we explore the energy and performance tradeoffs of these techniques. We also investigate the sensitivity of microprocessor performance and energy consumption to additional cache latency caused by leakage-reduction techniques.     

An improved statistical analysis of the least mean fourth (LMF) adaptive algorithm

The paper presents an improved statistical analysis of the least mean fourth (LMF) adaptive algorithm behavior for a stationary Gaussian input. The analysis improves previous results in that higher order moments of the weight error vector are not neglected and that it is not restricted to a specific noise distribution. The analysis is based on the independence theory and assumes reasonably slow learning and a large number of adaptive filter coefficients. A new analytical model is derived, which is able to predict the algorithm behavior accurately, both during transient and in steady-state, for small step sizes and long impulse responses. The new model is valid for any zero-mean symmetric noise density function and for any signal-to-noise ratio (SNR). Computer simulations illustrate the accuracy of the new model in predicting the algorithm behavior in several different situations.     

High-performance MIM capacitor using ALD high-k HfO/sub 2/-Al/sub 2/O/sub 3/ laminate dielectrics

For the first time, we successfully fabricated and demonstrated high performance metal-insulator-metal (MIM) capacitors with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate dielectric using atomic layer deposition (ALD) technique. Our data indicates that the laminate MIM capacitor can provide high capacitance density of 12.8 fF//spl mu/m/sup 2/ from 10 kHz up to 20 GHz, very low leakage current of 3.2 /spl times/ 10/sup -8/ A/cm/sup 2/ at 3.3 V, small linear voltage coefficient of capacitance of 240 ppm/V together with quadratic one of 1830 ppm/V/sup 2/, temperature coefficient of capacitance of 182 ppm//spl deg/C, and high breakdown field of /spl sim/6 MV/cm as well as promising reliability. As a result, the HfO/sub 2/-Al/sub 2/O/sub 3/ laminate is a very promising candidate for next generation MIM capacitor for radio frequency and mixed signal integrated circuit applications.     

Hydrogen annealing effect on DC and low-frequency noise characteristics in CMOS FinFETs

The hydrogen annealing process has been used to improve surface roughness of the Si-fin in CMOS FinFETs for the first time. Hydrogen annealing was performed after Si-fin etch and before gate oxidation. As a result, increased saturation current with a lowered threshold voltage and a decreased low-frequency noise level over the entire range of drain current have been attained. The low-frequency noise characteristics indicate that the oxide trap density is reduced by a factor of 3 due to annealing. These results suggest that hydrogen annealing is very effective for improving device performance and for attaining a high-quality surface of the etched Si-fin.