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51.
分子结构对增塑聚氯乙烯性能的影响 总被引:2,自引:0,他引:2
研究了聚合度、分子量分布和支化结构对增塑聚氯乙烯加工流变性能和物理力学性能的影响。结果表明,增塑PVC的加工流变性能随聚合度的增加而恶化;拓宽分子量分布和引入支化结构均有利于加工流变性能的提高;增塑PVC的拉伸强度随聚合度的增加而提高,而压缩永久变形却随之减小;分子量分布对物理力学性能的影响不大;支化PVC的拉伸强度略有下降。 相似文献
52.
JM Karski SJ Teasdale P Norman J Carroll K VanKessel P Wong MF Glynn 《Canadian Metallurgical Quarterly》1995,110(3):835-842
This prospective, double-blind, randomized trial assessed the effectiveness of high-dose tranexamic acid given in the preoperative period on blood loss in patients undergoing cardiopulmonary bypass. One hundred fifty patients scheduled to undergo cardiac operations with cardiopulmonary bypass were randomized into three groups of equal size. The first group received 10 gm of tranexamic acid intravenously over 20 minutes before sternotomy and a placebo infusion over 5 hours. The second group received 10 gm of tranexamic acid over 20 minutes and then another 10 gm infused intravenously over 5 hours. The control group received a placebo bolus and a placebo infusion over 5 hours (0.9% normal saline solution). The blood loss after the operation was measured at 6 hours and 24 hours. The homologous blood and blood products given during and up to 48 hours after operation were recorded. Eighteen percent of the control group patients shed more than 750 ml blood in 6 hours compared with only 2% in both tranexamic acid groups. Patients who shed more than 750 ml blood required 93% more red blood cell transfusions than patients without excessive bleeding. Tranexamic acid (10 gm) given intravenously in the period before cardiopulmonary bypass reduced blood loss over 6 hours by 50% and over 24 hours by 35%. Continued tranexamic acid infusion (10 gm over 5 hours) did not reduce bleeding further. There was no difference in the coagulation profile before operation between patients with and without excessive bleeding. However, coagulation tests done in the postoperative period indicated ongoing fibrinolysis and platelet dysfunction in patients with excessive bleeding. 相似文献
53.
Watanabe Y. Hing Wong Kirihata T. Kato D. DeBrosse J.K. Hara T. Yoshida M. Mukai H. Quader K.N. Nagai T. Poechmueller P. Pfefferl P. Wordeman M.R. Fujii S. 《Solid-State Circuits, IEEE Journal of》1996,31(4):567-574
This paper describes a 256 Mb DRAM chip architecture which provides up to ×32 wide organization. In order to minimize the die size, three new techniques: an exchangeable hierarchical data line structure, an irregular sense amp layout, and a split address bus with local redrive scheme in the both-ends DQ were introduced. A chip has been developed based on the architecture with 0.25 μm CMOS technology. The chip measures 13.25 mm×21.55 mm, which is the smallest 256 Mb DRAM ever reported. A row address strobe (RAS) access time of 26 ns was obtained under 2.8 V power supply and 85°C. In addition, a 100 MHz×32 page mode operation, namely 400 M byte/s data rate, in the standard extended data output (EDO) cycle has been successfully demonstrated 相似文献
54.
Dagan Feng Koon-Pong Wong Chi-Ming Wu Wan-Chi Siu 《IEEE transactions on information technology in biomedicine》1997,1(4):243-254
Positron emission tomography (PET) is an important tool for enabling quantification of human brain function. However, quantitative studies using tracer kinetic modeling require the measurement of the tracer time-activity curve in plasma (PTAC) as the model input function. It is widely believed that the insertion of arterial lines and the subsequent collection and processing of the biomedical signal sampled from the arterial blood are not compatible with the practice of clinical PET, as it is invasive and exposes personnel to the risks associated with the handling of patient blood and radiation dose. Therefore, it is of interest to develop practical noninvasive measurement techniques for tracer kinetic modeling with PET. In this paper, a technique is proposed to extract the input function together with the physiological parameters from the brain dynamic images alone. The identifiability of this method is tested rigorously by using Monte Carlo simulation. The results show that the proposed method is able to quantify all the required parameters by using the information obtained from two or more regions of interest (ROIs) with very different dynamics in the PET dynamic images. There is no significant improvement in parameter estimation for the local cerebral metabolic rate of glucose (LCMRGlc) if there are more than three ROIs. The proposed method can provide very reliable estimation of LCMRGlc, which is our primary interest in this study 相似文献
55.
An ordered dynamic channel assignment with reassignment (ODCAR) scheme is proposed, and its performance is studied in a highway microcellular radio environment. Channels are assigned in an ordered basis in conjunction with a minimax algorithm under cochannel interference constraints, to provide high capacity and to alleviate worst case channel congestion in each microcell. Simulation results show significant performance improvements in terms of channel utilization and probability of call failure, at the expense of an increase in complexity and call switching requirements 相似文献
56.
57.
Xiaofeng Liao Shizhong Yang Kwok-Wo Wong 《Dynamical Systems: An International Journal》2003,18(3):231-243
In this paper, the dynamical characteristics of hybrid bi-directional associative memory (BAM) neural networks with constant transmission delays are investigated. Without assuming the symmetry of synaptic connection weights and the monotonicity and differentiability of activation functions, the Lyapunov functionals are constructed and Halanay-type inequalities are respectively employed to derive the delay-independent sufficient conditions under which the networks converge exponentially to the equilibria associated with temporally uniform external inputs. Some examples are given to illustrate that the results are less conservative and less restrictive than the previously known results. 相似文献
58.
A microprocessor clock generator based on an analog phase-locked loop (PLL) is described for deskewing the internal logic control lock to an external system lock. This PLL is fully generated onto a 1.2-million-transistor microprocessor in 0.8-μm CMOS technology without the need for external components. It operates with a lock range from 5 to 110 MHz. The clock skew is less than 0.1 ns, with a peak-to-peak jitter of less than 0.3 ns for a 50-MHz system clock frequency 相似文献
59.
Degradation Behaviors of Metal-Induced Laterally Crystallized n-Type Polycrystalline Silicon Thin-Film Transistors Under DC Bias Stresses 总被引:1,自引:0,他引:1
Min Xue Mingxiang Wang Zhen Zhu Dongli Zhang Man Wong 《Electron Devices, IEEE Transactions on》2007,54(2):225-232
Device degradation behaviors of typical-sized n-type metal-induced laterally crystallized polycrystalline silicon thin-film transistors were investigated in detail under two kinds of dc bias stresses: hot-carrier (HC) stress and self-heating (SH) stress. Under HC stress, device degradation is the consequence of HC induced defect generation locally at the drain side. Under a unified model that postulates, the establishment of a potential barrier at the drain side due to carrier transport near trap states, device degradation behavior such as asymmetric on current recovery and threshold voltage degradation can be understood. Under SH stress, a general degradation in subthreshold characteristic was observed. Device degradation is the consequence of deep state generation along the entire channel. Device degradation behaviors were compared in low Vd-stress and in high Vd-stress condition. Defect generation distribution along the channel appears to be different in two cases. In both cases of SH degradation, asymmetric on current recovery was observed. This observation, when in low Vd-stress condition, is tentatively explained by dehydrogenation (hydrogenation) effect at the drain (source) side during stress 相似文献
60.
Dasgupta U. Wooi Gan Yeoh Chun Geik Tan Sheng Jau Wong Mori H. Singh R. Itoh M. 《Microwave Theory and Techniques》2002,50(11):2443-2452
An implementation of the IF section of WCDMA mobile transceivers with a set of two chips fabricated in an inexpensive 0.35-/spl mu/m two-poly three-metal CMOS process is presented. The transmit/receive chip set integrates quadrature modulators and demodulators, wide dynamic range automatic gain control (AGC) amplifiers, with linear-in-decibel gain control, and associated circuitry. This paper describes the problems encountered and the solutions envisaged to meet stringent specifications, with process and temperature variations, thus overcoming the limitations of CMOS devices, while operating at frequencies in the range of 100 MHz-1 GHz. Detailed measurement results corroborating successful application of the new techniques are reported. A receive AGC dynamic range of 73 dB with linearity error of less than /spl plusmn/2 dB and spread of less than 5 dB for a temperature range of -30/spl deg/C to +85/spl deg/C in the gain control characteristic has been measured. The modulator measurement shows a carrier suppression of 35 dB and sideband/third harmonic suppression of over 46 dB. The core die area of each chip is 1.5 mm/sup 2/. 相似文献