Cost Effective VLSI Architectures for Full-Search Block-Matching Motion Estimation Algorithm

In this paper, we present efficient VLSI architectures for full-search block-matching motion estimation (BMME) algorithm. Given a search range, we partition it into sub-search arrays called tiles. By fully exploiting data dependency within a tile, efficient VLSI architectures can be obtained. Using the proposed VLSI architectures, all the block-matchings in a tile can be processed in parallel. All the tiles within a search range can be processed serially or concurrently depending on various requirements. With the consideration of processing speed, hardware cost, and I/O bandwidth, the optimal tile size for a specific video application is analyzed. By partitioning a search range into tiles with appropriate size, flexible VLSI designs with different throughput can be obtained. In this way, cost effective VLSI designs for a wide range of video applications, from H.261 to HDTV, can be achieved.     

Effect of Bi and Sr concentrations on the formation of the 2223 phase in Bi-Pb-Sb-Sr-Ca-Cu-O materials, obtained under different conditions of thermal treatment

The superconducting properties and the phase and chemical composition of Bi _x Pb_0.3Sb_0.1Sr _y Ca₂Cu₃O_z (x=1.5, 1.6, and 1.7;y=1.9, 2.0, and 2.1) materials synthesized by one-step and multistep thermal treatments have been investigated. The multistep annealing between 825–875°C promotes the 2223 phase. The change of Bi concentration has little effect on the 2223 phase formation, regardless of the kind of thermal treatment used, but increasing the Sr concentration (y> 2) strongly inhibits this phase. It has also been established that the loss of Pb after synthesis depends on the initial Bi concentration. The loss of Pb decreases when the initial Bi content is lower.     

Kinetic study of the hydrolysis of isocyanic acid in the gas phase

The hydrolysis of isocyanic acid in the gaseous phase has been investigated at temperatures between 553 and 613 K by mass spectrometry and evaluated to obtain the corresponding kinetic data. The reaction order and reaction constant have been determined. Finally, the influence of water on the catalysed formation of melamine from isocyanic acid under the operating conditions employed has been investigated in order to determine whether there is a need to try the process gas.     

A numerical model for the dissolution of spherical particles in binary alloys under mixed mode control

A general numerical model is described for the dissolution kinetics of spherical particles in binary systems for any combination of first order reactions at the particle-matrix interface and long distance diffusion within the matrix. The model is applicable to both finite and infinite media and handles both complete and partial particle dissolution. It is shown that interfacial reactions can have a strong effect on the dissolution kinetics, the solute concentration at the particle-matrix interface and the solute concentration profile in the matrix.     

超薄SiO2层的热生长

隧道小孔中超薄ＳｉＯ２的生长是ＥＥＰＲＯＭ电路制造的关键工艺之一。采用ＳＵＰＲＥＭ－Ⅲ工艺模拟程序对超薄ＳｉＯ２的热生长进行了工艺模拟，经过大量的工艺实验及优化，确定了超薄ＳｉＯ２的最佳生长条件，生长出的ＳｉＯ２性能良好，完全可满足ＥＥＰＲＯＭ研制的要求。     

Experimental determination of thermal conductivity of apple and potato at different moisture contents

Thermal conductivity of apple and potato samples was measured by means of a specifically designed apparatus based on Fitch's method. The thermal conductivity was determined at various moisture contents at the sample mean temperature of 30 °C. As expected the conductivity decreases with the decrease in moisture content. Thermal conductivity data were correlated with moisture content using a straight line.     

High throughput VLSI DSP using replicated finite rings

This paper discusses strategies for implementing DSP systems using residue replication. The theory, recently introduced by two of the authors, uses formal polynomial ring mappings, from binary representations, to direct product ring implementation of integer processing arrays. The mapping produces completely independent computational arrays each computing over the same ring. This paper describes an architecture and processing array to implement, and take advantage of, the special computational ring structures that result from the mapping. A brief review of the theory and mapping techniques, is followed by the discussion of the architecture and VLSI design of an efficient inner product processing array using Fermat Primes.     

Dynamic programming implementation on array processor architectures

Dynamic Programming (DP) applies to many signal and image processing applications including boundary following, the Viterbi algorithm, dynamic time warping, etc. This paper presents an array processor implementation of generic dynamic programming. Our architecture is a SIMD array attached to a host computer. The processing element of the architecture is based on an ASIC design opting for maximum speed-up. By adopting a torus interconnection network, a dual buffer structure, and a multilevel pipeline, the performance of the DP chip is expected to reach the order of several GOPS. The paper discusses both the dedicated hardware design and the data flow control of the DP chip and the total array.This work was supported in part by the NATO, Scientific and Environmental Affairs Division, Collaborative Research Grant SA.5-2-05(CRG.960201)424/96/JARC-501.