Joint routing and channel assignment using online learning in cognitive radio networks

Cognitive radio networks (CRNs) are the solution for the problem of underutilizing the licensed spectrum for which there are more requests in the last couple of decades. In CRNs, Secondary users (SUs) are permitted to access opportunistically the licensed spectrum owned by primary users (PUs). In this paper, we address the problem of joint routing and channel assignment for several flows generated by source SUs to a given destination. We consider a more realistic model based on Markov modulated Poisson process for modeling the PUs traffic at each channel and the SUs try to exploit short lived spectrum holes between the PUs packets at the selected channel. The SUs want to cooperatively minimize the end-to-end delay of source SUs flows meanwhile the quality of service requirements of the PUs would be met. To consider partial observation of SUs about PUs activity at all channels and quick adaptation of SUs decisions to environment changes and cooperative interaction of SUs, we use decentralized partially observable markov decision process for modeling the problem. Then, an online learning based scheme is proposed for solving the problem. Simulation results show that the performance of the proposed method and the optimal method is close to each other. Also, simulation results show that the proposed method greatly outperforms related works at control of interference to the PUs while maintains the end-to-end delay of SU flows in a low level.

     

CPTR: conditional probability tree based routing in opportunistic networks

In opportunistic networks due to the inconsistency of the nodes link, routing is carried out dynamically and we cannot use proactive routes. In these networks, nodes use opportunities gained based on store-carry-forward patterns to forward messages. Every node that receives a message when it encounters another node makes decision regarding the forwarding or not forwarding the node encountered. In some previous methods, the recognition of whether encounter with current node is considered as an appropriate opportunity or not has been carried out based on the comparison of the probability of carrier node and the node encountered. In these methods, if the message is delivered to the encountered node, a better opportunity would be lost. To fight with this challenge we have posed CPTR method by using conditional probability tree method through which in addition to the probability of the delivery of carrier and encountered nodes’ message delivery, the opportunities for after encounter will be involved in messages’ forwarding. Results of simulation showed that the proposed method can improve the ratio of delivery and delay of message delivery compared to other similar methods in networks with limited buffer.     

Using Markov Learning Utilization Model for Resource Allocation in Cloud of Thing Network

Wireless Personal Communications - The integration of the Internet of Things (IoT) and cloud environment has led to the creation of Cloud of Things, which has given rise to new challenges in IoT...     

Low-power CMOS distributed amplifier using new cascade gain cell for high and low gain modes

A CMOS distributed amplifier (DA) with low-power and flat and high power gain (S₂₁) is presented. In order to decrease noise figure (NF) an RL terminating network used for the gate transmission line instead of single resistance. Besides, a flat and high S₂₁ is achieved by using the proposed cascade gain cell consist of a cascode-stage with bandwidth extension capacitor. In the high-gain mode, under operation condition of V _dd  = 1.2 V and the overall current consumption of 7.8 mA, simulation result shown that the DA consumed 9.4 mW and achieved a flat and high S₂₁ of 20.5 ± 0.5 dB with an average NF of 6.5 dB over the 11 GHz band of interest, one of the best reported flat gain performances for a CMOS UWB DA. In the low-gain mode, the DA achieved average S₂₁ of 15.5 ± 0.25 dB and an average NF of 6.6 dB with low power consumption (P_DC) of 3.6 mW, the lowest P_DC ever reported for a CMOS DA or LNA with an average gain better than 10 dB.     

Transient detection in COTS processors using software approach

This paper presents a software-based error detection scheme called enhanced committed instructions counting (ECIC) for embedded and real-time systems using commercial off-the-shelf (COTS) processors. The scheme uses the internal performance monitoring features of a processor, which provides the ability to count the number of committed instructions in a program. To evaluate the ECIC scheme, 6000 software induced faults are injected into a 32-bit Pentium® processor. The results show that the error detection coverage varies between 90.52% and 98.18%, for different workloads.     

Decimal SRT Square Root: Algorithm and Architecture

Given the popularity of decimal arithmetic, hardware implementation of decimal operations has been a hot topic of research in recent decades. Besides the four basic operations, the square root can be implemented as an instruction directly in the hardware, which improves the performance of the decimal floating-point unit in the processors. Hardware implementation of decimal square rooters is usually done using either functional or digit-recurrence algorithms. Functional algorithms, entailing multiplication per iteration, seem inadequate to use for decimal square roots, given the high cost of decimal multipliers. On the other hand, digit-recurrence square root algorithms, particularly SRT (this method is named after its creators, Sweeney, Robertson, and Tocher) algorithms, are simple and well suited for decimal arithmetic. This paper, with the intention of reducing the latency of the decimal square root operation while maintaining a reasonable cost, proposes an SRT algorithm and the corresponding hardware architecture to compute the decimal square root. The proposed fixed-point square root design requires n+3 cycles to compute an n-digit root; the synthesis results show an area cost of about 31K NAND2 and a cycle time of 40 FO4. These results reveal the 14 % speed advantage of the proposed decimal square root architecture over the fastest previous work (which uses a functional algorithm) with about a quarter of the area.     

A Perspective on Network Coding Based on Packet Length

Wireless Personal Communications - Network coding (NC) significantly increases communication opportunities and improves network performance. The focus of most research is on performance analysis...     

Optimal characterization of a microwave transistor using grey wolf algorithms

Analog Integrated Circuits and Signal Processing - Modern time microwave stages require low power consumption, low size, low-noise amplifier (LNA) designs with high-performance measures. These...     

A Noisy Channel Tolerant Image Encryption Scheme

In this paper, we present an image encryption scheme that has the capability to tolerate noisy effects of a wireless channel. This means if the encrypted image data is corrupted by channel noise up to a certain level, correct decryption is possible with some distortion. The proposed image encryption scheme relies on some very interesting properties of orthogonal matrices containing columns that form a set of orthonormal basis vectors. Besides being tolerant to noisy channels, the proposed scheme also provides good security against well-known cryptographic attacks as demonstrated in this paper by a number of experimental results and security analysis.