Frequency tunable metallo-dielectric structure for backscattering reduction

Electromagnetic scattering behaviour of a superstrate loaded metallo-dielectric structure based on Sierpinski carpet fractal geometry is reported. The results indicate that the frequency at which backscattering is minimum can be tuned by varying the thickness of the superstrate. A reduction in backscattered power of /spl sim/44 dB is obtained simultaneously for both TE and TM polarisations of the incident field.     

Characterization and profile optimization of SiGe pFETs onsilicon-on-sapphire

We present the details of the fabrication, electrical characterization, and profile optimization of a SiGe pFET on silicon-on-sapphire (SOS) technology. The results show that the SiGe pFETs have higher low-field mobility (μ_eff), transconductance (g_m), and cutoff frequency (f_T) than a comparable Si pFET. At low temperature (85 K), a secondary peak is observed in the linear g_m of the SiGe pFETs and is attributed to hole confinement in the SiGe channel. The effect of reducing the SOS film thickness on the mobility and short-channel performance is studied. A low-frequency noise study shows significant improvement in the SiGe pPETs over comparable Si pFETs, and is attributed to a lower sampling of interface trap density caused by the band offset at the oxide interface due to SiGe. Drain Induced Back Channel Inversion (DIBCI) is shown to occur in short gate length devices, resulting in high off-state leakage current through conduction at the back silicon-sapphire interface. The paper also discusses important optimization issues in the design of 0.25-μm gate length SiGe pFETs. A novel structure is proposed which optimizes the threshold voltage, maximizes hole confinement gate voltage range and cutoff frequency, while at the same time minimizing DIBCI to make the design usable to gate lengths as short as 0.25 μm     

5-GHz 32-bit integer execution core in 130-nm dual-V/sub T/ CMOS

A 32-bit integer execution core containing a Han-Carlson arithmetic-logic unit (ALU), an 8-entry /spl times/ 2 ALU instruction scheduler loop and a 32-entry /spl times/ 32-bit register file is described. In a 130 nm six-metal, dual-V/sub T/ CMOS technology, the 2.3 mm/sup 2/ prototype contains 160 K transistors. Measurements demonstrate capability for 5-GHz single-cycle integer execution at 25/spl deg/C. The single-ended, leakage-tolerant dynamic scheme used in the ALU and scheduler enables up to 9-wide ORs with 23% critical path speed improvement and 40% active leakage power reduction when compared to a conventional Kogge-Stone implementation. On-chip body-bias circuits provide additional performance improvement or leakage tolerance. Stack node preconditioning improves ALU performance by 10%. At 5 GHz, ALU power is 95 mW at 0.95 V and the register file consumes 172 mW at 1.37 V. The ALU performance is scalable to 6.5 GHz at 1.1 V and to 10 GHz at 1.7 V, 25/spl deg/C.     

Pseudo-Parallel Datapath Structure for Power Optimal Implementation of 128-pt FFT/IFFT for WPAN

An optimal implementation of 128-Pt FFT/IFFT for low power IEEE 802.15.3a WPAN using pseudo-parallel datapath structure is presented, where the 128-Pt FFT is devolved into 8-Pt and 16-Pt FFTs and then once again by devolving the 16-Pt FFT into 4×4 and 2×8. We analyze 128-Pt FFT/IFFT architecture for various pseudo-parallel 8-Pt and 16-Pt FFTs and an optimum datapath architecture is explored. It is suggested that there exists an optimum degree of parallelism for the given algorithm. The analysis demonstrated that with a modest increase in area one can achieve significant reduction in power. The proposed architectures complete one parallel-to-parallel (i.e., when all input data are available in parallel and all output data are generated in parallel) 128-point FFT computation in less than 312.5 ns and thereby meet the standard specification. The relative merits and demerits of these architectures have been analyzed from the algorithm as well as implementation point of view. Detailed power analysis of each of the architectures with a different number of data paths at block level is described. We found that from power perspective the architecture with eight datapaths is optimum. The core power consumption with optimum case is 60.6 MW which is only less than half of the latest reported 128-point FFT design in 0.18u technology. Furthermore, a Single Event Upset (SEU) tolerant scheme for registers is also explored. The SEU tolerant scheme will not affect the performance, however, there is an increase power consumption of about 42 percent. Apart from the low power consumption, the advantages of the proposed architectures include reduced hardware complexity, regular data flow and simple counter based control.     

A High-Precision Quasi-optical Polarizer for Zeeman Splitting Observations

A series of grooved dielectric quarter-wave plates was made for radio astronomical Zeeman splitting observations at millimeter wavelengths. To meet the stringent requirements on reflection and polarization purity, a design method was formulated based on optimization of multiple reflections. The method solves the problem of achieving low reflections for both polarization components while attaining high purity of circular polarization. Several plates have been manufactured, tested, and used successfully for astronomical observations.     

CSRS-MAC: Cluster Based Synchronous Radio Scheduling MAC Protocol Using Carrier Sense Multiple Access for Wireless Sensor Network

Wireless Personal Communications - Wireless sensor network is gaining popularity due to its large-scale deployment in Internet of Things. The constraints of resources influence the protocol design...     

Improving the photocatalytic performance of TiO2 via hybridizing with graphene

In this paper an improvement in the photocatalytic performance of TiO₂ was carried out via hybridizing with graphene. Graphene-TiO₂ (GR-TiO₂)nanocomposites with different weight addition ratios of graphene oxide (GO) have been prepared via a facile microwave irradiation of GO and tetrabutyl titanate in isopropyl alcohol. Raman spectroscopy (RS), X-ray diffraction (XRD), scanning electron microscopy (SEM), transmission electron microscopy (TEM), UV-visible spectroscopy (UV-vis), Fourier transform infrared spectra (FTIR), energy dispersive X-ray spectroscopy (EDX) and photoluminescence spectra (PL) are employed to determine the properties of the samples. Microwave irradiation can heat the reactant to a higher temperature in a short time, simultaneously GO is reduced to graphene and TiO₂ nanoparticles grown on the surface of GR. GR-TiO₂ nanocomposites synthesized via this approach have efficient electron conductivity in GR, resulting in a reduced electron-hole recombination rate. Among the synthesized nanocomposites, GT-8wt% exhibited the best photocatalytic activity toward photocatalytic degradation of MB. Our current work provides a new insight for the fabrication of GR-TiO₂ nanocomposites within a short reaction time and also explains the mechanism of photocatalysis employing radical and hole scavengers.     

Noise performance comparison for third and fourth order cascaded sigma-delta modulators having parameter tolerance errors

A parameter tolerance, signal to noise ratio comparison is made between the MASH third order sigma-delta modulator structure and a new fourth order cascaded structure. The fourth order structure meets the required performance specification with wider parameter tolerances, allowing easier integration using hybrid CMOS technology.<>     

A triple-mode hexa-standard reconfigurable TI cross-coupled ΣΔ modulator

Hardware reconfigurability is an attractive solution for modern multi-standard wireless systems. This paper analyses the performance and implementation of an efficient triple-mode hexa-standard reconfigurable sigma-delta (∑?) modulator designed for six different wireless communication standards. Enhanced noise-shaping characteristics and increased digitisation rate, obtained by time-interleaved cross-coupling of ∑? paths, have been utilised for the modulator design. Power/hardware efficiency and the capability to acclimate the requirements of wide hexa-standard specifications are achieved by introducing an advanced noise-shaping structure, the dual-extended architecture. Simulation results of the proposed architecture using Hspice shows that the proposed modulator obtains a peak signal-to-noise ratio of 83.4/80.2/67.8/61.5/60.8/51.03 dB for hexa-standards, i.e. GSM????????/Bluetooth/GPS/WCDMA/WLAN/WiMAX standards with significantly less hardware and low operating frequency. The proposed architecture is implemented in 45 nm CMOS process using a 1 V supply and 0.7 V input range with a power consumption of 1.93 mW. Both architectural- and transistor-level simulation results prove the effectiveness and feasibility of this architecture to accomplish multi-standard cellular communication characteristics.     

The generation-recombination mechanism of charge transport in a thin-film CdS/CdTe heterojunction

An n-CdS/p-CdTe heterostructure is studied. The heterostructure is obtained using the sequential growth of CdS and CdTe layers by electrochemical deposition and closed-space sublimation, respectively. The measured current-voltage characteristics are interpreted in the context of the Sah-Noyce-Shokley generation-recombination model for the depletion layer of a diode structure. The theory quantitatively agrees with the experimental results.