Borate Distribution in Stabilized Stainless-Steel Slag

Disintegration of stainless-steel slag during cooling is caused by the β→γ transformation of dicalcium silicate (2CaO·SiO₂ or C₂S). It is well established that disintegration can be avoided by borate additions, which are commonly believed to stabilize the high-temperature polymorphs by forming a solid solution with C₂S. In this study, the borate distributions in slowly cooled synthetic and industrial slag samples are determined. The slag microstructures are characterized using electron probe microanalysis (EPMA), quantitative X-ray diffraction (QXRD), and wavelength dispersive spectroscopy (WDS). The results show that only a limited fraction of the added borates forms a solid solution with the C₂S phase, while the main fraction is found in a calcium borosilicate phase. In combination with literature data, this suggests that slag stabilization involves more than the chemical stabilization of the high-temperature C₂S polymorphs.     

Design and Tool Flow of Multimedia MPSoC Platforms

This paper surveys components that are useful to build programmable, predictable, composable, and scalable multiprocessor-system-on-a-chip (MPSoC) multimedia platforms that can deliver high performance at high power-efficiency. A design-time tool flow is proposed to exploit all forms of parallelism on such platforms. As a first proof of concept, the flow is used to parallelize a relatively simple video standard on a platform consisting of off-the-shelf components. As a second proof of concept, we present the design of a high-performance platform with state-of-the-art components. This platform targets real-time H.264 high-definition video encoding at an estimated power consumption of 700 mW.

Pattern Componentization: The Factory Example

Can Design Patterns be turned into reusable components? To help answer this question, we have performed a systematic study of the standard design patterns. One of the most interesting is Abstract Factory, for which we were indeed able to build a reusable component fulfilling the same needs as the original pattern. This article presents the component’s design and its lessons for the general issue of pattern componentization.     

Consumer attitudes towards hypoallergenic apples that alleviate mild apple allergy

The development of genetically modified (GM) foods with benefits for consumers may be more acceptable than GM foods with benefits that accrue to industry or producers. The Santana apple is a novel hypoallergenic product suitable for many apple allergic consumers with mild symptomology. The Santana also needs fewer pesticides to be applied in production. A survey was conducted among consumers who bought the Santana in a large-scale “sales pilot”. The Santana was perceived to be beneficial by many apple allergic consumers. Non-allergic consumers were less positive about genetically modified hypoallergenic apples. Overall, traditional breeding was the preferred production strategy, although acceptance of genetic modification as a process did increase with increasing perceived personal benefit associated with products, in particular those which were “medically-related”, or perceived to reduce allergic reactions. Consumer preferences for reduced pesticide usage were also found, although this was more contingent on type of production processes applied.     

Componentization: the Visitor example

Patterns provide a vocabulary and catalog for common design solutions but are not reusable software. Through advanced object-oriented language mechanisms it is possible to simplify the application developer's job by turning certain patterns into fully reusable solutions.     

Guidance of Loop Ordering for Reduced Memory Usage in Signal Processing Applications

Data dominated signal processing applications are typically described using large and multi-dimensional arrays and loop nests. The order of production and consumption of array elements in these loop nests has huge impact on the amount of memory required during execution. This is essential since the size and complexity of the memory hierarchy is the dominating factor for power, performance and chip size in these applications. This paper presents a number of guiding principles for the ordering of the dimensions in the loop nests. They enable the designer, or design tools, to find the optimal ordering of loop nest dimensions for individual data dependencies in the code. We prove the validity of the guiding principles when no prior restrictions are given regarding fixation of dimensions. If some dimensions are already fixed at given nest levels, this is taken into account when fixing the remaining dimensions. In most cases an optimal ordering is found for this situation as well. The guiding principles can be used in the early design phases in order to enable minimization of the memory requirement through in-place mapping. We use real life examples to show how they can be applied to reach a cost optimized end product. The results show orders of magnitude improvement in memory requirement compared to using the declared array sizes, and similar penalties for choosing the suboptimal ordering of loops when in-place mapping is exploited.