Routing Protocols in Delay Tolerant Networks: Comparative and Empirical Analysis

Wireless Personal Communications - A Delay Tolerant Network (DTN) is a network capable of handling long delays and data loss efficiently in various challenged scenarios and environments. Owing to...     

Smart City Healthcare Cyber Physical System: Characteristics,Technologies and Challenges

Wireless Personal Communications - The recent pandemic has demanded a strong and smart healthcare system which can monitor the patients efficiently and handle the situation that arises from the...     

A low-power up-conversion CMOS mixer for 22-29-GHz ultra-wideband applications

A double-balanced, low-power, and low-voltage dual-gate up-conversion mixer working at K-band is designed and fabricated in the UMC 130-nm logic CMOS process. The mixer achieves a 3-dB conversion-gain bandwidth of 1.8 GHz at the input IF port and a 3-dB conversion-gain bandwidth of 10 GHz at the output RF port. The mixer achieves an output referred 1-dB compression point as high as -5.8 dBm and an output referred third-order intercept point as high as 5.8 dBm, while consuming 8.0 mW from a 1.2-V supply. This study demonstrates that the implementation of low-power mixers operating in the 22-29-GHz band for ultra-wideband automotive radar applications is possible in low-cost and low-voltage logic CMOS technology.     

Comprehensive review for energy efficient hierarchical routing protocols on wireless sensor networks

Wireless Networks - In recent years, wireless sensor networks (WSNs) have played a major role in applications such as tracking and monitoring in remote environments. Designing energy efficient...     

Enhanced ground bounce noise reduction in a low-leakage CMOS multiplier

In this paper, various parameters are used to reduce leakage power, leakage current and noise margin of circuits to enhance their performance. A multiplier is proposed with low-leakage current and low ground bounce noise for the microprocessor, digital signal processors (DSP) and graphics engines. The ground bounce noise problem appears when a conventional power-gating circuit transits from sleep-to-active mode. This paper discusses a reduction in leakage current in the stacking power-gating technique by three modes – sleep, active and sleep-to-active. The simulation results are performed on a 4 × 4 carry-save multiplier for leakage current, active power, leakage power and ground bounce noise, and comparison made for different nanoscales. Ground bounce noise is limited to 90%. The leakage current of the circuit is decimated up to 80% and the active power is reduced to 31%. We performed simulations using cadence virtuoso 180 and 45 nm at room temperature at various supply voltages.     

Design of efficient lightweight strategies to combat DoS attack in delay tolerant network routing

Delay tolerant networks (DTNs) are characterized by delay and intermittent connectivity. Satisfactory network functioning in a DTN relies heavily on co-ordination among participating nodes. However, in practice, such co-ordination cannot be taken for granted due to possible misbehaviour by relay nodes. Routing in a DTN is, therefore, vulnerable to various attacks, which adversely affect network performance. Several strategies have been proposed in the literature to alleviate such vulnerabilities—they vary widely in terms of throughput, detection time, overhead etc. One key challenge is to arrive at a tradeoff between detection time and overhead. We observe that the existing table-based reactive strategies to combat Denial-of-service (DoS) attacks in DTN suffer from two major drawbacks: high overhead and slow detection. In this paper, we propose three secure, light-weight and time-efficient routing algorithms for detecting DoS attacks (Blackhole and Grey-hole attacks) in the Spray & Focus routing protocol. The proposed algorithms are based on use of a small fraction of privileged (trusted) nodes. The first strategy, called TN, outperforms the existing table-based strategy with 20–30 % lesser detection time, 20–25 % higher malicious node detection and negligible overhead. The other two strategies, CTN_MI and CTN_RF explore the novel idea that trusted nodes are able to utilize each others’ information/experience using their long range connectivity as and when available. Simulations performed using an enhanced ONE simulator reveals that investing in enabling connectivity among trusted nodes (as in CTN_RF) can have significant performance benefits.     

C60 Concentration Influence on MEH-PPV:C60 Bulk Heterojunction-Based Schottky Devices

We have investigated the effect of C60 concentration on the performance of poly[2-methoxy-5-(2′-ethylhexoxy-p-phenylene vinylene] (MEH-PPV):C60 blend-based Schottky barrier-based devices. Incorporation of C60 in MEH-PPV leads to a red shift and the reduction of intensity in MEH-PPV absorption spectra. The appearance of a C60 characteristic band in the Raman spectra of the composites indicates the presence of C60 in the blends. A FESEM study reveals that the addition of C60 significantly modifies the surface morphology of the blend films. However, higher concentrations (>?5 wt.%) results in agglomeration of C60 particles. Dark I–V measurements allow us to extract various diode parameters including barrier height, ideality factor, and saturation current. Profound variations have been observed in the dominant charge carrier transport mechanism for different C60 concentrations. A photoresponse study demonstrates the enhancement in the photocurrent with the increase in the C60 concentration up to 5 wt.%. Beyond this concentration, agglomeration impedes exciton dissociation and charge transport, which results in a decrease in the photocurrent. Finally, an impedance spectroscopy analysis has been extensively carried out to estimate the internal device parameters, such as junction resistance, capacitance and carrier lifetime. The correlation between these parameters and I–V curves has been established.     

Technologies for Ultradynamic Voltage Scaling

Energy efficiency of electronic circuits is a critical concern in a wide range of applications from mobile multimedia to biomedical monitoring. An added challenge is that many of these applications have dynamic workloads. To reduce the energy consumption under these variable computation requirements, the underlying circuits must function efficiently over a wide range of supply voltages. This paper presents voltage-scalable circuits such as logic cells, SRAMs, ADCs, and dc–dc converters. Using these circuits as building blocks, two different applications are highlighted. First, we describe an H.264/AVC video decoder that efficiently scales between QCIF and 1080p resolutions, using a supply voltage varying from 0.5 V to 0.85 V. Second, we describe a 0.3 V 16-bit microcontroller with on-chip SRAM, where the supply voltage is generated efficiently by an integrated dc–dc converter.      

Micro- and nanofabrication processes for hybrid synthetic and biological system fabrication

The application of micro- and nanofabrication processes to the development of hybrid synthetic and biological systems may enable the production of new devices such as controllable transporters, gears, levers, micropumps, or microgenerators powered by biological molecular motors. However, engineering these hybrid devices requires fabrication processes that are compatible with biological materials such as kinesin motor proteins and microtubules. In this paper, the effects of micro- and nanofabrication processing chemicals and resists on the functionality of casein, kinesin, and microtubule proteins are systematically examined to address the important missing link of the biocompatibility of micro- and nanofabrication processes needed to realize hybrid system fabrication. It is found that both casein, which is used to prevent motor denaturation on surfaces, and kinesin motors are surprisingly tolerant of most of the processing chemicals examined. Microtubules, however, are much more sensitive. Exposure to the processing chemicals leads to depolymerization, which is partially attributed to the pH of the solutions examined. When the chemicals were diluted in aqueous buffers, a subset of them no longer depolymerized microtubules and in their diluted forms still worked as resist removers. This approach broadens the application of micro- and nanofabrication processes to hybrid synthetic and biological system fabrication.     

Elimination of bipolar induced drain breakdown and singletransistor latch in submicron PD SOI MOSFET

For the first time, we report the combined application of a SiGe source and a delta-doped p⁺ region in a PD SOI MOSFET to minimize the impact of floating body effect on both the drain breakdown voltage and the single transistor latch. Our results demonstrate that the proposed SOI structure exhibits as large as 200% improvement in the breakdown voltage and is completely immune to single transistor latch when compared to the conventional SOI MOSFET thus improving the reliability of these structures in VLSI applications