On codes defined by bio-operations

We consider the classes of ⊕$\oplus$-codes and ⊗$\otimes$-codes, which are superclasses of outfix and hyper-codes, respectively. These restrictions are based on the synchronized insertion operation, which serves as a model for the gene rearrangement function in certain unicellular organisms. We investigate the classes of ⊕$\oplus$-codes and ⊗$\otimes$-codes from a theoretical perspective, examine their relationships with traditional code classes and consider related decidability problems.     

On the removal of shadows from images

This paper is concerned with the derivation of a progression of shadow-free image representations. First, we show that adopting certain assumptions about lights and cameras leads to a 1D, gray-scale image representation which is illuminant invariant at each image pixel. We show that as a consequence, images represented in this form are shadow-free. We then extend this 1D representation to an equivalent 2D, chromaticity representation. We show that in this 2D representation, it is possible to relight all the image pixels in the same way, effectively deriving a 2D image representation which is additionally shadow-free. Finally, we show how to recover a 3D, full color shadow-free image representation by first (with the help of the 2D representation) identifying shadow edges. We then remove shadow edges from the edge-map of the original image by edge in-painting and we propose a method to reintegrate this thresholded edge map, thus deriving the sought-after 3D shadow-free image.     

On the analysis of stochastic divide and conquer algorithms

This paper develops general tools for the analysis of stochastic divide and conquer algorithms. We concentrate on the average performance and the distribution of the running time of the algorithm. As a special example we analyse the average performance and the running time distribution of the (2k + 1)-median version of Quicksort. Online publication October 13, 2000.     

Organized knowledge sharing with book-centered Web sites: An architecture, implementation and analysis

For educators, the World Wide Web offers a valuable technology for knowledge sharing. It can complement more traditional approaches to knowledge sharing such as books and lectures. Here, we identify and differentiate three major approaches for Web-based knowledge sharing: course-centered sites, subject-centered sites, and book-centered sites. A rationale for book-centered sites, those developed to facilitate students’ and instructors’ efforts in courses that use the book, is advanced. We introduce an architecture of features that can guide developers of such sites. This is illustrated by a book-centered site implemented according to the architecture. Several sites for introductory business computing books are compared and contrasted in terms of the architecture, suggesting ways in which each can be extended. This revised version was published online in July 2006 with corrections to the Cover Date.     

Sequential architecture models for Prolog: A performance comparison

In this paper we investigate the relation between architectural support for Prolog and performance. We will show that partial support for tags does perform as well as full support, but it only reduces the execution time by approximately 10%. With respect to special addressing modes, auto address modification (post/pre increment, decrement on loads and stores) only yields a cycle reduction of approximately 6% and the introduction of a single shadow register set yields around 8%. Combining these optimizations, a performance gain of 20 to 25% can be achieved, depending on the memory system. Usingvliw techniques, which exploit instruction-level parallelism, the performance can be doubled, using three processing elements. Two processing elements already provide a significant speedup, but the use of four processing elements is not justified if we compare the gain in performance with the cost of the extra hardware. In general we observe only a small performance improvement (around 20%) when moving fromrisc to special-purposerisc architectures, an improvement which can also be achieved by applying advanced compiler technology, such as compiler optimization, optimizations forwam, and optimal scheduling techniques forvliw architectures. Unfortunately these hardware and software effects do not add up, as a better compiler reduces the effect of hardware support. Finally, the cycle time is essential for comparing the performance of different (micro)-architectures, but it is not always clear what the effects of the different tradeoffs are on the maximum achievable cycle time.