Particle-based multiple irregular volume rendering on CUDA

In this paper, we describe an improved particle-based volume rendering (PBVR) technique for previewing a large irregular volume dataset using the CUDA architecture. This technique allows for opaque and emissive particles to render translucent volumes without visibility sorting. Our GPU acceleration of PBVR provides the multi-volume rendering feature while remaining compatible with both regular and irregular volumes. We also reduce the memory cost required for storing all sub-pixel values by proposing a pixel repetition technique for a large sub-pixel level. By adjusting the repetition level, we achieved a very smooth level of detail (LOD) control for trading quality for speed. Our work demonstrates a full-detail rendering rate from 5 to 10 fps for irregular volume data with mega-scale cell numbers on an NVIDIA GeForce 8800GTS.     

Cooperation of categorical and behavioral learning in a practical solution to the abstraction problem

Real robots should be able to adapt autonomously to various environments in order to go on executing their tasks without breaking down. They achieve this by learning how to abstract only useful information from a huge amount of information in the environment while executing their tasks. This paper proposes a new architecture which performs categorical learning and behavioral learning in parallel with task execution. We call the architectureSituation Transition Network System (STNS). In categorical learning, it makes a flexible state representation and modifies it according to the results of behaviors. Behavioral learning is reinforcement learning on the state representation. Simulation results have shown that this architecture is able to learn efficiently and adapt to unexpected changes of the environment autonomously. Atsushi Ueno, Ph.D.: He is a research associate in the Artificial Intelligence Laboratory at the Graduate School of Information Science at the Nara Institute of Science and Technology (NAIST). He received the B.E., the M.E., and the Ph.D. degrees in aeronautics and astronautics from the University of Tokyo in 1991, 1993, and 1997 respectively. His research interest is robot learning and autonomous systems. He is a member of Japan Association for Artificial Intelligence (JSAI). Hideaki Takeda, Ph.D.: He is an associate professor in the Artificial Intelligence Laboratory at the Graduate School of Information Science at the Nara Institute of Science and Technology (NAIST). He received his Ph.D. in precision machinery engineering from the University of Tokyo in 1991. He has conducted research on a theory of intelligent computer-aided design systems, in particular experimental study and logical formalization of engineering design. He is also interested in multiagent architectures and ontologies for knowledge base systems.     

Shear viscosity of the B phase of superfluid3He

The shear viscosity (T) in the Balian-Werthamer (BW) state of superfluid ³ He is calculated variationally throughout the region 0t 1(t=T/T _c) from the transport equation for Bogoliubov quasiparticles. Coherence factors are treated exactly in the calculation of the collision integral. The numerical result for =_s= _s(T)/_n(T_c) agree very well with experiment in the range 0.8t1.0. Analytic expressions = 0.577 (1–1.0008t) and =1–(23/64) [=(T)/k _B T] are obtained in the low-temperature region and in the vicinity ofT _c, respectively. From the numerical analysis it is shown that the latter equation is valid only in the temperature range 0.9997t1.0.Supported by the Research Institute for Fundamental Physics, Kyoto University.     

A high‐performance sorting algorithm for multicore single‐instruction multiple‐data processors

Many sorting algorithms have been studied in the past, but there are only a few algorithms that can effectively exploit both single‐instruction multiple‐data (SIMD) instructions and thread‐level parallelism. In this paper, we propose a new high‐performance sorting algorithm, called aligned‐access sort (AA‐sort), that exploits both the SIMD instructions and thread‐level parallelism available on today's multicore processors. Our algorithm consists of two phases, an in‐core sorting phase and an out‐of‐core merging phase. The in‐core sorting phase uses our new sorting algorithm that extends combsort to exploit SIMD instructions. The out‐of‐core algorithm is based on mergesort with our novel vectorized merging algorithm. Both phases can take advantage of SIMD instructions. The key to high performance is eliminating unaligned memory accesses that would reduce the effectiveness of SIMD instructions in both phases. We implemented and evaluated the AA‐sort on PowerPC 970MP and Cell Broadband Engine platforms. In summary, a sequential version of the AA‐sort using SIMD instructions outperformed IBM's optimized sequential sorting library by 1.8 times and bitonic mergesort using SIMD instructions by 3.3 times on PowerPC 970MP when sorting 32 million random 32‐bit integers. Also, a parallel version of AA‐sort demonstrated better scalability with increasing numbers of cores than a parallel version of bitonic mergesort on both platforms. Copyright © 2011 John Wiley & Sons, Ltd.     

Numerical study on the effect of heat loss upon the critical marangoni number in a half-zone liquid bridge

In a half-zone (HZ) liquid bridge, flow exhibits a transition from a two-dimensional steady to a three-dimensional oscillatory flow if the Marangoni number Ma exceeds a critical value Ma_c, or ΔT>ΔT_c. In case of high Prandtle number fluids, the Mac obtained in the numerical simulations deviated significantly from the ones by the experiments. One of the causes of the difference is due to the heat loss over the free surface. Most of past researches neglected effects of the heat loss through an interface of the liquid bridge. Recently several experimental and analytical works reported that the critical condition is significantly affected by the heat loss. The present study aims to include the effects of the heat loss upon the Ma_c. As the result, the calculated Ma_c agrees well with the experiment for a high Pr fluid.     

Quantum Monte Carlo Device Simulation of Nano-Scaled SOI-MOSFETs

Quantum transport properties of nano-scaled SOI-MOSFETs are investigated based on a quantum Monte Carlo (MC) device simulation. The quantum mechanical effects are incorporated in terms of a quantum correction of potential in the well-developed particle MC computational techniques. The ellipsoidal multi-valleys of silicon conduction band are also considered in the simulation. First, the validity of the quantum MC technique is verified by comparing the simulated results with a self-consistent Schrödinger-Poisson solution at thermal equilibrium. Then, we apply the technique to non-equilibrium and quasi-ballistic quantum transport in nano-scaled SOI-MOSFETs.     

Objective Oriented Multistage Ring Shear Test for Shear Strength of Landslide Soil

Ring shear tests were conducted on five samples of different nature with a modified Imperial College type ring shear machine. The three different testing methods used, (1) individual sample testing for each normal stress, (2) increasing load multistage ring shear test, and (3) reducing load multistage ring shear test, all showed similar effective residual internal friction angle for the samples, irrespective of testing method. However, effective residual shear intercept was different according to the testing methodology. The internal friction angle did not vary, particularly after the first minimum point in the stress displacement curve, although the residual shear intercept decreased with increase in the displacement. The thickness of the shearing zone increased along with the displacement. The remolded peak shear strength for saturated conditions at field dry density varied with the consolidation history. Measurement of remolded peak shear strength was possible in a single sample using the increasing load multistage ring shear test at normal consolidation. The equilibrium water content of the sample after the ring shear test was nearly equal to the plastic limit.     

Semantic Web: A road to the knowledge infrastructure on the internet

In this article, I describe the basic technologies for Semantic Web and relationship between Semantic Web and Knowledge Representation in Artificial Intelligence. Semantic Web is planned as an extension of the current web in order to help cooperation between computers and humans, i.e., computers and humans are expected to understand each other in the knowledge level. I first describe the vision of the Semantic Web, then introduce the current Semantic Web technologies, i.e., RDF, RDFS, and OWL. I describe relationship between the trend of Semantic Web and Knowledge Representation, and clarify challenges and difficulties of Semantic Web from the point of view of Knowledge Representation. Hideaki Takeda: He is a professor at National Institute of Informatics (NII) and a professor in Department of Informatics at the Graduate University of Advanced Studies (Sokendai). He received his Ph.D. from the University of Tokyo in 1991. His research interest in computer science includes ontology engineering, community informatics and knowledge sharing systems.     

Partial redundancy elimination for access expressions by speculative code motion

We present a new memory access optimization for Java to perform aggressive code motion for speculatively optimizing memory accesses by applying partial redundancy elimination (PRE) techniques. First, to reduce as many barriers as possible and to enhance code motion, we perform alias analysis to identify all the regions in which each object reference is not aliased. Secondly, we find all the possible barriers. Finally, we perform code motions in three steps. For the first step, we apply a non‐speculative PRE algorithm to move load instructions and their following instructions in the backwards direction of the control flow graph. For the second step, we apply a speculative PRE algorithm to move some of them aggressively before the conditional branches. For the third step, we apply our modified version of a non‐speculative PRE algorithm to move store instructions in the forward direction of the control flow graph and to even move some of them after the merge points. We implemented our new algorithm in our production‐level Java just‐in‐time compiler. Our experimental results show that our speculative algorithm improves the average (maximum) performance by 13.1% (90.7%) for jBYTEmark and 1.4% (4.4%) for SPECjvm98 over the fastest algorithm previously described, while it increases the average (maximum) compilation time by 0.9% (2.9%) for both benchmark suites. Copyright © 2004 John Wiley & Sons, Ltd.