High Areal Capacitance of N‐Doped Graphene Synthesized by Arc Discharge

The lack of cost effective, industrial‐scale production methods hinders the widespread applications of graphene materials. In spite of its applicability in the mass production of graphene flakes, arc discharge has not received considerable attention because of its inability to control the synthesis and heteroatom doping. In this study, a facile approach is proposed for improving doping efficiency in N‐doped graphene synthesis through arc discharge by utilizing anodic carbon fillers. Compared to the N‐doped graphene (1–1.5% N) synthesized via the arc process according to previous literature, the resulting graphene flakes show a remarkably increased doping level (≈3.5% N) with noticeable graphitic N enrichment, which is rarely achieved by the conventional process, while simultaneously retaining high turbostratic crystallinity. The electrolyte ion storage of synthesized materials is examined in which synthesized N‐doped graphene material exhibits a remarkable area normalized capacitance of 63 µF cm^?2. The surprisingly high areal capacitance, which is superior to that of most carbon materials, is attributed to the synergistic effect of extrinsic pseudocapacitance, high crystallinity, and abundance of exposed graphene edges. These results highlight the great potentials of N‐doped graphene flakes produced by arc discharge in graphene‐based supercapacitors, along with well‐studied active exfoliated graphene and reduced graphene oxide.     

Process windows for low-temperature Au wire bonding

The process windows are presented for low-temperature Au wire bonding on Au/Ni/Cu bond pads of varying Au-layer thicknesses metallized on an organic FR-4 printed circuit board (PCB). Three different plating techniques were used to deposit the Au layers: electrolytic plating, immersion plating, and immersion plating followed by electrolytic plating. Wide ranges of wire bond force, bond power, and bond-pad temperature were used to identify the combination of these processing parameters that can produce good wire bonds, allowing the construction of process windows. The criterion for successful bonds is no peel off for all 20 wires tested. The wire pull strengths and wire deformation ratios are measured to evaluate the bond quality after a successful wire bond. Elemental and surface characterization techniques were used to evaluate the bond-pad surfaces and are correlated to wire bondability and wire pull strength. Based on the process windows along with the pull strength data, the bond-pad metallization and bonding conditions can be further optimized for improved wire bondability and product yields. The wire bondability of the electrolytic bond pad increased with Au-layer thickness. The bond pad with an Au-layer thickness of 0.7 μm displayed the highest bondability for all bonding conditions used. The bondability of immersion bond pads was comparable to electrolytic bond pads with a similar Au thickness. Although a high temperature was beneficial to wire bondability with a wide process window, it did not improve the bond quality as measured by wire pull strength.     

Design of Scannable Non‐uniform Planar Array Structure for Maximum Side‐Lobe Reduction

In this letter, we propose a novel design scheme for an optimal non‐uniform planar array geometry in view of maximum side‐lobe reduction. This is implemented by a thinned array using a genetic algorithm. We show that the proposed method can maintain a low side‐lobe level without pattern distortion during beam steering.     

A charge-trapping-based technique to design low-voltage BiCMOSlogic circuits

New BiCMOS logic circuits employing a charge trapping technique are presented. The circuits include an XOR gate and an adder. Submicrometer technologies are used in the simulation and the circuits' performances are comparatively evaluated with the CMOS and that of the recently reported circuits. The proposed circuits were fabricated using a standard 0.8-μm BiCMOS process. The experimental results obtained from the fabricated chip have verified the functionality of the proposed logic gates     

1.5 V high-speed electrostatic discharge free BiCMOS digitalcircuit

A novel circuit design that effectively eliminates the need for input protection circuits is described. Besides having an excellent electrostatic discharge (ESD) robustness, the simulation results have shown that this design outperforms current BiCMOS circuits in terms of speed, power, crossover capacitance, and chip area for a wide range of load capacitances, power supply voltages and technologies. The proposed circuit remains functional after an ESD test     

In vivo Doppler shift measurements using multimode fiber-opticcatheters

A new fiber-optic catheter for in vivo blood-flow measurements has been developed. The catheter is designed to measure blood flow in both the forward (toward the catheter tip) and reverse (away from the catheter tip) flow directions. It consists of two multimode optical fibers with core diameter of 50 μm and cladding diameter of 125 μm. One fiber transmits the laser beam into blood and the other receives the backscattered light from the erythrocytes within the probe volume. In the flow experiment, it was found that the flow within the boundary layer is indeed laminar and, hence, the relationship between the Doppler shift frequencies and the flow velocities is linear, thereby making the linear calibration possible for predicting the free stream flow velocity. Plots of the maximum shift frequency (frequency at which the Doppler spectrum disappeared into the noise spectrum) against the flow velocities are found to be more linear in both the forward and reverse flow directions than that of the dominant shift frequency (frequency with the highest amplitude). These results were reaffirmed by the numerical flow simulation along the catheter side wall     

Scalar quantisation of LSF parameters using vector measurement

A new form of line spectral frequency (LSF), bounded line spectral frequency, is presented. It is shown that the new representation is more efficient than the direct line spectral frequency and the differential line spectral frequency (DLSF). By using a vector measure, the scalar quantisation of tenth-order linear predictive coding (LPC) parameters can be coded at 28 bit/frame with a transparent quantisation quality     

Effects of high temperature annealing on the device characteristics of Ga0.52In0.48P/GaAs and Al0.52In0.48P/GaAs heterojunction bipolar transistors

GaInP/GaAs and AlInP/GaAs heterojunction bipolar transistor (HBT) structures were grown by low pressure metalorganic vapor phase epitaxy and annealed at various temperatures up to 675°C for 15 min. Subsequent comparisons with HBTs fabricated on both annealed and unannealed control samples showed no effects for annealing up to and including 575°C, but significant changes in the electrical characteristics were observed at an annealing temperature of 675°C. For the GaInP/GaAs devices, the base current increased by a significant amount, reducing the gain and increasing the base current ideality factor from 1.07 to 1.9. Photoluminescence and electrical measurements on the structures indicated that both the emitter and base were affected by an increase in the recombination times in those regions. These effects were attributed to an out-diffusion of hydrogen from the base during annealing. The emitter of the AlInP/GaAs HBT was affected less by the hydrogen diffusion because of the larger bandgap. These observations have important implications for device performance dependence on the details of the temperature/time profile subsequent to the base growth.     

Study on stacking faults and microtwins in wide bandgap II-VI semiconductor heterostructures grown on GaAs

ZnMgSSe and ZnSSe layers grown on GaAs substrates with GaAs buffer layers by molecular beam epitaxy have been examined by transmission electron microscopy (TEM). The depth level at which paired triangular stacking faults are nucleated in the ZnMgSSe/GaAs heterostructure has been investigated by using the plan-view TEM technique. It has been found that in the ZnMgSSe/GaAs heterostructure the nucleation of the paired stacking faults occurs within a range of depth which starts at the II-VI/GaAs interface and ends at a level that is above the interface by about 120 nm. The dominant type of defects in ZnSSe layers, which have the single triangular shape, has been identified to be microtwins by high resolution TEM.