An Effective Test and Diagnosis Algorithm for Dual‐Port Memories

This paper proposes a test algorithm that can detect and diagnose all the faults occurring in dual‐port memories that can be accessed simultaneously through two ports. In this paper, we develop a new diagnosis algorithm that classifies faults in detail when they are detected while the test process is being developed. The algorithm is particularly efficient because it uses information that can be obtained by test results as well as results using an additional diagnosis pattern. The algorithm can also diagnose various fault models for dual‐port memories.     

The influence of solder volume and pad area on Sn–3.8Ag–0.7Cu and Ni UBM reaction in reflow soldering and isothermal aging

This paper examines various aspects of SAC (Sn–3.8Ag–0.7Cu wt.%) solder and UBM interactions which may impact interconnection reliability as it scales down. With different solder joint sizes, the dissolution rate of UBM and IMC growth kinetics will be different. Solder bumps on 250, 80 and 40 μm diameter UBM pads were investigated. The effect of solder volume/pad metallization area (V/A) ratio on IMC growth and Ni dissolution was investigated during reflow soldering and solid state isothermal aging. Higher V/A ratio produced thinner and more fragmented IMC morphology in SAC solder/Ni UBM reflow soldering interfacial reaction. Lower V/A ratio produced better defined IMC layer at the Ni UBM interface. When the ratio of V/A is constant, the IMC morphology and growth trend was found to be similar. After 250 h of isothermal aging, the IMC growth rate of the different bump sizes leveled off. No degradation in shear strength was observed in these solder bump after 500 h of isothermal aging.     

Effect of plasma treatment of Au-Ni-Cu bond pads on process windows of Au wire bonding

The wire bondability of Au-Ni-Cu bond pads with different Au plating schemes, including electrolytic and immersion plates, are evaluated after plasma treatment. The plasma cleaning conditions, such as cleaning power and time, are optimized based on the process window and wire pull strength measurements for different bond pad temperatures. Difference in the efficiency of plasma treatment in improving the wire bondability for different Au plates is identified. The plasma-cleaned bond pads are exposed to air to evaluate the recontamination process and the corresponding degradation of wire pull strength. The changes in bond pad surface characteristics, such as surface free energy and polar functionality, with exposure time are correlated to the wire pull strength, which in turn provides practical information about the shelf life of wire bonding after plasma cleaning.     

Design of Reader Baseband Receiver Structure for Demodulating Backscattered Tag Signal in a Passive RFID Environment

In this paper, we present a demodulation structure suitable for a reader baseband receiver in a passive radio frequency identification (RFID) environment. In a passive RFID configuration, an undesirable DC‐offset phenomenon may appear in the baseband of the reader receiver, which can severely degrade the performance of the extraction of valid information from the received tag signal. To eliminate this DC‐offset phenomenon, the primary feature of the proposed demodulation structures for the received FM0 and Miller subcarrier signals is to reconstruct the signal corrupted by the DC‐offset phenomenon by creating peak signals from the corrupted signal. It is shown that the proposed method can successfully detect valid data, even when the received baseband signal is distorted by the DC‐offset phenomenon.     

Fabrication of Multiscale Gradient Polymer Patterns by Direct Molding and Spatially Controlled Reflow

Size variations of pattern spacing as well as gradient control of the as‐formed polymeric pattern via a spatially controlled reflow process are presented. Micro‐ and nanopatterns of polymethyl methacrylate (PMMA) in the form of line‐and‐space strips are first generated by capillary force lithography (CFL), and the residual layers are removed by ashing process. Subsequently, the exposed PMMA strips underwent a controlled reflow process above the glass transition temperature (T_g) while heating single or both sides of the substrate either in parallel to the line pattern (parallel reflow) or perpendicular to the line pattern (perpendicular reflow). As a result of this controlled reflow, a linear or a parabolic profile of pattern spacing is achieved depending on the heating mode. Furthermore, multiscale gradient patterns are formed with the spacing ranging from 98 nm to 4.23 μm (a difference of two orders of magnitude) in a single patterned layer using the original micropattern of 16 μm width and 8 μm spacing. In order to explain reflow behaviors, a simple theoretical model relating the normalized pattern width to the polymer viscosity is derived based on a leveling kinetics of polymer melt. Also, gradient PMMA channels are fabricated and bonded to a glass substrate, which are used to flow a liquid inside the channels by capillarity‐driven flow.     

Pulsewidth Modulation Circuits Using CMOS OTAs

This paper presents three pulsewidth modulation modulators using CMOS operational transconductance amplifiers. They consist of a ramp integrator and current-tunable Schmitt triggers. Prototype circuits built using discrete components exhibited that their duty cycles are linearly controllable. Because of their simple structure, the proposed modulators can be easily fabricated in a monolithic integrated circuit.     

能实现高压输出的抽头电感升压稳压器

当您面对产生比可用电源电压更高的稳定电压任务时,可以考虑升压稳压器。虽然升压转换器在理论上能产生比其输入更高的几乎任何电压,但实际的考虑把输出限制为对其施加的电压的大约8倍。为了产生更高的电压,可考虑使用抽头电感升压拓扑结构。图1展示了某种转换器的实现,它把3V输入提高到了100Vdc。稳压器芯片的连接类似于传统升压转换器的连接,但为了达到很高的升压比,该设计使用了L1,即一个1:6匝数比的抽头电感。图2中的波形示出了输入电压、电源开关IC1输出端(5号引脚SW)的电压、整流二极管D1的阳极电压。如同任何升压电路一样,当IC1…     

Superposition Coding with Unequal Error Protection for the Uplink of Overloaded DS-CDMA System

The overloaded CDMA schemes exploited in direct sequence CDMA (DS-CDMA) systems are mainly to accommodate a greater number of users than the available spreading factor N. In this paper, a superposition coding CDMA (SPC-CDMA) with unequal error protection (UEP) is proposed as one of the overloaded CDMA schemes for the next generation mobile communication systems. It exploits the available power control in most base stations to adapt the transmitted power of active users in the uplink channel. In this scheme, the active users are divided into G groups and each group consists of K users. The K users share the same spreading sequence and are distinguished by different received power levels. At the receiver side, the system first performs despreading for group detection followed by multiuser receiver to estimate the K user signals in each group. It is shown through simulations that better performance are achieved compared to the conventional DS-CDMA and existing overloaded collaborative spreading CDMA (CS-CDMA) schemes, in additive white Gaussian noise (AWGN) and fading channels. Hence, the proposed scheme maximizes the system capacity K-fold compared to conventional DS-CDMA system without requiring extra spreading codes, with average signal to noise ratio (SNR) cost of only 1dB and 2 dB over AWGN and fading channels respectively at BER of 10^?3. On the other hand, for the same N, K and power constraints, SPC-CDMA scheme achieves twofold increase in data rate with 0.7 and 4 dB gains over AWGN and fading channels respectively, compared with overloaded CS-CDMA scheme in the same system capacity. In addition, the proposed scheme can also attain different levels of UEP for different users?? requirements by adjusting their fractions of transmitted powers.     

Fine‐Grained FSMD Power Gating Considering Power Overhead

As a fine‐grained power gating method for achieving greater power savings, our approach takes advantage of the finite state machine with a datapath (FSMD) characteristic which shows sequential idleness among subcircuits. In an FSMD‐based power gating, while only an active subcircuit is expected to be turned on, more subcircuits should be activated due to the power overhead. To reduce the number of missed opportunities for power savings, we deactivated some of the turned‐on subcircuits by slowing the FSMD down and predicting its behavior. Our microprocessor experiments showed that the power savings are close to the upper bound.